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    Question about loop filter of CDR/PLL

    Hi,
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    As I know this type of loop filter is very common, it can found from lot of textbooks and thesis.
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    But what is the purpose of above graph(a connection to node between resistor and capacitor)?
    Is the transfer function still same as 1 path current injection? if not how to find the transfer function?
    I have search alot of paper and textbook and I didn't found any discussion about it.


    Thank you.
    sorry for my poor english.

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    Re: Question about loop filter of CDR/PLL

    We need more information on the application to be certain but I would guess C1 is the charge reservoir from the lower charge pump and the R1/C2 are a simple RC filter. In general, two charge pumps driving each other doesn't make sense so that 'enable' signal must have some control over which is producing the error voltage. The topology is quite different to the top schematic.

    Brian.
    PLEASE - no friends requests or private emails, I simply don't have time to reply to them all.
    It's better to share your questions and answers on Edaboard so we can all benefit from each others experiences.



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    Re: Question about loop filter of CDR/PLL

    Having frequency and phase lock-loops with different transfer characteristic can make sense to improve the lock behavior. Building it with two charge pumps is just an implementation detail that shouldn't be overrated. Presume you know what's the difference between frequency and phase detector and what's their purpose in a PLL.

    Without guessing too much, you can assume that both charge pumps are activated mutual exclusively, the frequency detector signal is only active in unlocked state and the phase detector in locked state. A standard PLL with combined phase/frequency detector can be expected to activate the charge pump up/down outputs in unlocked state with 100 % duty cycle. The present design does the same, but has the option to tune the frequency detector transfer characteristic differently.

    To find the transfer characteristic, you need the quantitative parameters of all blocks and components.



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    Re: Question about loop filter of CDR/PLL

    It seems that frequency detector here is used to bring two signals close to each other. When frequency difference is small then phase detector is enabled to make a phase lock.



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    Re: Question about loop filter of CDR/PLL

    Quote Originally Posted by betwixt View Post
    We need more information on the application to be certain but I would guess C1 is the charge reservoir from the lower charge pump and the R1/C2 are a simple RC filter. In general, two charge pumps driving each other doesn't make sense so that 'enable' signal must have some control over which is producing the error voltage. The topology is quite different to the top schematic.

    Brian.
    Thanks you for the reply,

    pic.1
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    pic.2
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    pic.3
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    pic.4
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    I would like to design a clock and data recovery circuit, and I am confused by the dual loop system. Usually phase locked loop text book only discuss about single loop system as we see from pic.1 and the filter function is pic2. I would like to try to do a loop analysis about pic3's dual loop clock and data recovery architecture.
    I have done single loop pll behavioral simulation using matlab (Pic.4).
    I have no idea how to do the simulation using architecture pic.4, which have 2 charge pump connected to difference node on a single loop filter ,
    and what the loop filter function should be ? (with 2 current injected into the loop filter, lets say I1 for PLL and I2 for FLL)
    any reference about this?

    reference:
    pic3 taken from https://ieeexplore.ieee.org/document/4415629

    thanks you.



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    Re: Question about loop filter of CDR/PLL

    I agree with the loop filter analysis, except for the erroneous R2 which should be R1. Why can't you perform the same analysis for the charge pump feeding C2 in this circuit? You get a similar second order transfer function, but without a zero.

    Frequency detector mode and switching between FD and PD mode requires a state machine, also in the single loop PFD configuration and can't be modelled by a simple linear transfer function.



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    Re: Question about loop filter of CDR/PLL

    Yeah, the R2 should be replaced by R1 which looks like the pic below (taken from the Dean Banerjee PLL).
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    Quote Originally Posted by FvM View Post
    Why can't you perform the same analysis for the charge pump feeding C2 in this circuit? You get a similar second order transfer function, but without a zero.
    Sorry I don't get the point, do you mean I can run the loop analysis of the dual loop system as one loop system?

    Thank you



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    Re: Question about loop filter of CDR/PLL

    As previously stated, the charge pumps will be activated alternatively, you can calculate transfer functions for both detectors separately.



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  9. #9
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    Re: Question about loop filter of CDR/PLL

    Quote Originally Posted by FvM View Post
    As previously stated, the charge pumps will be activated alternatively, you can calculate transfer functions for both detectors separately.
    I will try to do the analysis in this way
    Thank you.

    any alternative methods or ideas are welcome



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