engr_joni_ee
Advanced Member level 3
Hi,
I am writing testbench for a custom axi stream fifo which I have found online. It runs on ZYNQ board but I need to simulate it to understand it's function. In the testbench I have send four packets at slave input s00_axis_tdata when s00_axis_tready is '1'. The signal s00_axis_tvalid remain at '1' during the four packets and there is a s00_axis_tlast signal which is high only at the last data i.e. fourth packet.
At the output which is master side, it should send out same four packets but the data out m00_axis_tdata values are not the same as s00_axis_tdata. Also the signal m00_axis_tlast come at the third not at fourth data. The source code along with testbench is attached. Can someone please help in fining bug in the testbench ?
I am writing testbench for a custom axi stream fifo which I have found online. It runs on ZYNQ board but I need to simulate it to understand it's function. In the testbench I have send four packets at slave input s00_axis_tdata when s00_axis_tready is '1'. The signal s00_axis_tvalid remain at '1' during the four packets and there is a s00_axis_tlast signal which is high only at the last data i.e. fourth packet.
At the output which is master side, it should send out same four packets but the data out m00_axis_tdata values are not the same as s00_axis_tdata. Also the signal m00_axis_tlast come at the third not at fourth data. The source code along with testbench is attached. Can someone please help in fining bug in the testbench ?