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HDL simulation help to understand the function of verilog file

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engr_joni_ee

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Hi,

I am writing testbench for a custom axi stream fifo which I have found online. It runs on ZYNQ board but I need to simulate it to understand it's function. In the testbench I have send four packets at slave input s00_axis_tdata when s00_axis_tready is '1'. The signal s00_axis_tvalid remain at '1' during the four packets and there is a s00_axis_tlast signal which is high only at the last data i.e. fourth packet.

At the output which is master side, it should send out same four packets but the data out m00_axis_tdata values are not the same as s00_axis_tdata. Also the signal m00_axis_tlast come at the third not at fourth data. The source code along with testbench is attached. Can someone please help in fining bug in the testbench ?
 

Attachments

  • axis_fifo_v1_0.v.txt
    8.8 KB · Views: 42
  • axis_fifo_v1_0_tb.vhd.txt
    6.7 KB · Views: 55
  • Untitled.png
    Untitled.png
    54.2 KB · Views: 89

You need to change the stim_proc to be synchronous to the clock, not use absolute time. Otherwise your stimulus will change 1 delta before the clock, and on the waveform it looks as though the signals are changing 1 clock too early.
Instead of


Code VHDL - [expand]
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wait for 200 ns;



use this instead


Code VHDL - [expand]
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procedure wait_for_clks(signal clk : std_logic;
                               n   : integer := 1 );
begin
  for i in 1 to n loop
    wait until rising_edge(clk);
  end loop;
end procedure;
 
....
 
s00_axis_tdata  <= x"00000002";  
wait_for_clks(s00_axis_aclk, 2);
 
s00_axis_tdata  <= x"00000004"; 
wait_for_clks(s00_axis_aclk, 2);
 
--etc



Also - do not drive your slave and master signals from the same process. They are separate interfaces, so drive them independently.
 

Hi,

Yes now it works. I have send four TDATA data packets at the slave side with TVALID high for the four packets and TLAST high only for the last packet of slave. I get the same TDATA out at the master interface with VALID high for four data packets but TLAST of the master does not go low even after the last packet. The design is already tested on the ZYNQ board. I am trying to understand it's function. If there is no data in the FIFO then TLAST of the master should be zero but still it is high. Any explanation on this ? The updated testbench and the simulation is attached.
 

Attachments

  • axis_fifo_v1_00.v.txt
    8.8 KB · Views: 38
  • Untitled_01.png
    Untitled_01.png
    32.2 KB · Views: 93
  • axis_fifo_v1_00_tb.vhd.txt
    4.5 KB · Views: 34

Given the way tlast is generated (from the output of a memory) the last value assigned is the final value after it's sent and is not updated by any code to force it back to low after the last beat.

You could force it low by adding a test for tvalid && tready && tlast.

Regardless you shouldn't even look at tlast unless you have a tvalid and tready active.
 

its quite normal for blocks to have all the outputs staying the same after tvalid drops. if everything should be gated with tvalid and tready.
 

Hi,
Is there any requirement on TLAST in AXI Stream that it has to come after any of the 2 power n (i.e., 2, 4, 8, 16 or 32 etc ) or it can come after any number of packet ?
 

Hi,
Is there any requirement on TLAST in AXI Stream that it has to come after any of the 2 power n (i.e., 2, 4, 8, 16 or 32 etc ) or it can come after any number of packet ?

I think you are misunderstanding what a packet is.
A clock cycle where tvalid and tready are high together is an AXI transaction and "information" is transfered. "Information" covers tdata, tkeep, tstrb, tid, tdest and tlast (you do not have to use all of these signals)
A packet covers one or more axi transactions.
tlast marks the last transaction in a packet.

A packet is just an abstracted piece of information. eg. An ethernet packet, SRIO packet, PCIE packet, Mr Engineers super transport packet etc. A packet could be 1 or more bytes of data. If you have a 32 bit interface, you can only transfer 4 bytes per clock cycle. This means you will likely need several transactions to carry an entire packet Tlast marks where the packet ends. (eg, a full size ethernet frame is 1538 bytes, which means you will need 385 transactions to transfer it all. tlast = '0' for the first 384 transactions, and '1' on 385.)
 

A packet covers one or more axi transactions. tlast marks the last transaction in a packet.

I guess you mean that a packet may contain one or more data bytes and tlast indicate end of packet. The AXI transaction happen when tlast comes in the end of packet. In my case tdata is 32bit wide which is a simple counter and tlast comes on every 8th counter value which means that each packet contains 32 x 4 = 128 bytes, right ?
 

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