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ModelSim - How to force a struct type written in SystemVerilog?

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oho

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I'm still new to SystemVerilog, and I'm following the examples written in the book SystemVerilog for Design but Stuart Sutherland.
The first examples use struct for the data variables, and when I try to simulate using ModelSim, I can't use force. I tried forcing single elements, but it gives me the error:
Code:
Error: (vsim-3592) signal_force : Fields of user-defined types are not supported
and when I try to force the whole struct, I get this error:
Code:
# Cannot specify entire record value.
# ** Error: (vsim-4011) Invalid force value: {{32'h0054F321 32'h0043E210 8'h21}} 0.

I'm talking about simple structs like this one:
Code:
typedef struct packed {
    reg [31:0] address;
    reg [31:0] data;
    reg [7:0] opcode;
} instruction_word_t;
and this one:
Code:
package definitions;
    parameter VERSION = "1.1";
    typedef enum {ADD, SUB, MUL} opcodes_t;
    typedef struct {
        logic [31:0] a, b;
        opcodes_t opcode;
    } instruction_t;

    function automatic [31:0] multiplier (input [31:0] a,b);
        return a * b;
    endfunction
endpackage

I want to know how can I use force for such signals, is it even possible? And what is the right way to set them?

Thanks!
 

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