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Which package of Flyback controller has the lowest RTH(JA) value in our case?

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treez

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Hello,

We have designed a 5W, 24V Offline Flyback SMPS (240VAC input).
We are using a TNY287 controller which also comprises the switching FET.
There are three different package types of the TNY287.. the SOIC8, PDIP and ESOP.

We do not have room for a heatsink. As such, we are wondering which package will have the best thermal withstand, the PDIP, or the ESOP?

We realise that the ESOP has the lower Rth(JA) figure. However, that Rth(JA) figure (from pg 12 of the datasheet) concerns a single sided PCB. Though we have a double sided PCB, and so we suspect that the PDIP will actually end up having the lower RTH(JA) value, since the PDIP has metal legs which go right through the PCB, and get soldered to thermal copper pours on top and bottom layers.
So do you agree, that in our case, the PDIP will have the lower RTH(JA) value?

Please find attached the view of the layout with PDIP, and then with ESOP (red is top copper, blue is bottom copper)


TNY287 datasheet:-
https://ac-dc.power.com/sites/default/files/product-docs/tinyswitch-4_family_datasheet.pdf
 

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The heat slug on the ESOP will give you the best thetaJC
to the PCB ground plane, if you take advantage of this
then the thetaJA (effective) of the PCB-mounted IC will
be much superior to what lead conduction alone would
give you. This, not bare-package, unmounted thetaJA, is
the real deal.

I'd go with max thermal via density in the heat slug pad
(why only 9?) to drive the heat conduction to the back
more effectively. Also, the topside electrical connection
to the heat slug pad should be stiffer I think. On my POL
chips we used the heat slug as the -primary- electrical
connection to chip GND and using pins only gave a much
inferior conduction losses and some peculiar ground bounce
related behaviors (e.g. falling edge jitter). Might put this
to the mfr's in-house applications engineers to see whether
the ESOP takes similar advantage of the copper chunk's
general goodness, or is simply a single down bond (or
none, but conductive die attach) that's all inconsequential
for low side switch performance (net) and ground integrity.
 
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Thanks, i only put 9 thermal vias in the heat pad, because we are worried about wicking of solder through the thermal vias.
(they are 0.3mm diameter).
I did wonder if we could stop wicking by putting solder resist covering the bottom side outlet of the thermal via?
This point seems to be contested either way in past discussions.
The bottom side does not sit on a heatsink or anything.
 

Don't see how solder wicking is any better with 9 vias than
25, unless it's really a sparse statistical yield problem. Mask
the back and sweat the front, and call any wicking a heat-
throw bonus?

If solder wicks out on the bottom and impacts nothing,
what then is the harm?

Convection from two sides beats convection from one unless
there is nil airflow on the second. On the other hand if "top
side" is what gets the lousy air, second face would be huge
improvement.
 
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Thanks, good points, i see what you mean. We were worried about the actual solder thats needed to bond the part to the heat pad getting wicked away in such quantity that there isnt a good solder bond (& hence heat path) to the
thermal pad itself.
I mean we coudl address this by making the solder paste thicker on the heat pad than other pads on the board, but then that would make the stencil much more exppensive.

- - - Updated - - -

I must admit though , after your great points, i do believe an increase from 9 is in order.
 
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