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    Exclusion Layers for Dummy Metal Fill

    Hello,

    I am doing dummy metal fill for a layout.

    I have to add exclusion layers for metal fill not to be put in my circuit path - I need BOTH drawing exclusion layers AND via exclusion layers - they are both in the process I am using - TSMC. So do I need MEXCL(d1 to d8,for all metal 8 layers) AND the via layers to do exclusion ?

    Is this correct ?

    Thank you.

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    Re: Exclusion Layers for Dummy Metal Fill

    It might be that excluding a given metal layer will also
    prevent adjacent vias (else they would be malformed).

    But that assumes a certain logic in the fill rules and I'd
    bet there is specific guidance for you somewhere in the
    PDK docs-pile.



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    Re: Exclusion Layers for Dummy Metal Fill

    As I know, there are no DRC rule check for VIA density, right?
    And technically, if your working process has required fill BOTH metal and via, and in order to protect the sensitive circuits, you have to fill all dummy exclusion layer (metal, diff (OD), poly, and via (as you said))



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  4. #4
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    Re: Exclusion Layers for Dummy Metal Fill

    Quote Originally Posted by quyleanh View Post
    As I know, there are no DRC rule check for VIA density, right?
    And technically, if your working process has required fill BOTH metal and via, and in order to protect the sensitive circuits, you have to fill all dummy exclusion layer (metal, diff (OD), poly, and via (as you said))
    Update: there are no DRC rule check for VIA density --> I was wrong.
    There are actually VIA density rule check for via stack. And from 40nm technology, we also have dummy fill for via.



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