# bit pattern generator in Cadence Virtuoso

1. ## bit pattern generator in Cadence Virtuoso

Hi,

how to generate pattern data like:
0000
1000
0100
1100
0010
....
1111

by changing one variable "State", where
State = 0 at 0000
State = 1 at 1000
State = 2 at 0100
...
State = 15 at 1111

The task is to cheks S-parameters of 4 -bit digital attenuator.

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2. ## Re: bit pattern generator in Cadence Virtuoso

Last time I had to do this, was for a lot wider and deeper
and we used veriloga to build a pattern generator (for
Spectre simulation of tens of kGates worth of high speed
logic, handcrafted gates, blah blah).

The header and footer were common, and a vector set
was PERL formatted from the customer's source vectors
and then "cat header body footer >pattern.va", stuff that
below the symbol and veriloga views.

There's probably slicker ways to go about it in a more
digital or mixed-signal flow; for that job, stdCellLib was
just half as fast as it needed to be and analog was the
only way to get it done.

Now you could also do something simple like 4 voltage
sources and each set up as a table(State) function for
DC.

I have also used conditionals and math in voltage sources,
like you can get a bit value from a binary field by logic-as-math.

And I am in possession of a "volts2word8" veriloga widget, code
below (you can make your own symbol/veriloga view to house
it, I would expect). Just ignore the upper bits (or revise code
for only 4, whatever you like).

 Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 // VerilogA //     FUNCTION: Voltage to 8 bits //      VERSION: 0 //      AUTHORS: Joe Mama //           ON: whenever // // Description: Uses input voltage as input word and makes parallel 8 bit word output //  255Volts on vin = 11111111 on dout<7:0> // `include "constants.h" `include "discipline.h" `define NUM_BITS   8   module volts2word8 (vin,vdd,vss,dout); input vin,vdd,vss; voltage vin,vdd,vss; output   [`NUM_BITS-1:0] dout; voltage  [`NUM_BITS-1:0] dout; real b; integer i,n; analog begin     b=V(vin);     generate i (`NUM_BITS-1, 0) begin         n=0;         if (b > (1<

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