Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Paper showing intrinsic gain vs. minimum channel length evolution?

Status
Not open for further replies.

spectrallypure

Member level 3
Joined
Dec 10, 2007
Messages
56
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
Belgium
Activity points
1,889
Hi! Does anybody know of any recent paper/book showing the evolution of transistor intrinsic gain (gm*ro) with minimum channel length (=technology node)?

So far I've only found the graph below [1], but I'm looking for other references showing the same trend (i.e. that things get better in 22nm and below (FinFETs)).

Thanks in advance for any help!

[1] Holt, "Moore’s Law: A Path Going Forward", ISSCC'16

intrinsic_gain_vs_Lmin.jpg
 

There's a lot more to it than just u0CoxW/L (and three, at
least, moving at once for different influences).

Advanced technologies add all sorts of features to get an
"acceptable" reliability - LDD and halo details in the source
region can degrade gm a lot (you'll see RF folks fight for
their own, "not digital", transistor since they don't care
about DC leakage in an "off" device and can't stand source
resistance).
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top