Alauddin123
Newbie level 5
Hi All,
I have been working on FPGAs and know that how important I/O delays are in order for the device to work in external environment .
But to assign its value i have found like some people prefer input delay as 75% of clk_period and output delay as 25%.
What is actuall logic behind this ? can any one explain.
If this values doesn't make any sense then what is the general way of assigning the values ?
I have been working on FPGAs and know that how important I/O delays are in order for the device to work in external environment .
But to assign its value i have found like some people prefer input delay as 75% of clk_period and output delay as 25%.
What is actuall logic behind this ? can any one explain.
If this values doesn't make any sense then what is the general way of assigning the values ?
