flote21
Advanced Member level 1
Hello guys,
I am wondering about a signal integrity issue with a 100MHz clk generated by an FPGA.
This is the set up:
- FPGA generates a 100MHZ square signal with 50% of duty cycle.
- The IO constraint is LVCMOS 3.3V.
- The PCB track has a length of 20cm and it finished in a Sub-D25 connector. The track has a series termination resistor (Rt).
In the next pic you can see the problem:
It does not matter the value of the Rt, the CLK signal always looks like that. So it has a 1.5V offset and it has an amplitude around 800mV.
What do you think it is happening? I should set up a special constraint in the FPGA side to get this clock like a square signal with an amplitude of 3.3V?
Greetings
I am wondering about a signal integrity issue with a 100MHz clk generated by an FPGA.
This is the set up:
- FPGA generates a 100MHZ square signal with 50% of duty cycle.
- The IO constraint is LVCMOS 3.3V.
- The PCB track has a length of 20cm and it finished in a Sub-D25 connector. The track has a series termination resistor (Rt).
In the next pic you can see the problem:
It does not matter the value of the Rt, the CLK signal always looks like that. So it has a 1.5V offset and it has an amplitude around 800mV.
What do you think it is happening? I should set up a special constraint in the FPGA side to get this clock like a square signal with an amplitude of 3.3V?
Greetings