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Timing during Synthesis: Max clock frequency

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Alexxk

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Hi guys!

I am working on a digital part of a mixed signal design.
I am using LFoundry 150nm technology. When I synthesize my design with a fclock of 1Ghz with the typical library I can meet the timing, but when using the wort lib (not even the worst150degree, the worst just uses a reduced VDD) i get a WNS of -300ps. I am still a beginner in ASIC design but what I have read here so far is that it is common practice to use the worst lib for synthesis. Can I trust my circuit to work at 1Ghz If I take care that the VDD doesnt drop so the cells behave like the typical lib describes? Since this is a academic project, would be an increase in VDD a solution (to get to the parameters of the BEST library)?
I allready identified the critical path, so the worst case would be to alter my design there perform that calculations in two clock cylces, but nevertheless I would liek to have a deeper understanding about synthesis and which libs to use!

Thank you very much!

Alex
 

you are not interpreting worst/best VDD as it should be interpreted. VDD is beyond your control, it is not a knob you can play with. you supply the nominal voltage, whatever that is for the process. Yet, VDD distribution internal to your circuit is not perfect. Some places will end up receiving VDD*0.9 or some similar drop. That is why we make sure the circuit passes timing on the worst case and yet we always provide nominal VDD to the circuit. You can overshoot, of course, but that is not the norm.
 
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    Alexxk

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Thanks a lot!
Sadly I still couldnt meet timing with some more pipelining since the FFs are so slow in that technology (450ps propagation delay under worst)
 

Since there are certainly things you cannot model, you should
use worst-as-sensible models for timing until you can.

Are you at liberty to redesign the DFFs for your interests? In
my experience standard cell libraries are not made to push
performance; DFFs have internal clock stages that add to
CLK-Q delay (this is probably your main problem), may have
made choices you don't like regarding the balance between
setup and hold interval requirements (you would prefer zero
setup, and eat some hold time because you appear to have
plenty). Making a "bare clocked" DFF that receives aligned,
complementary CK,CKb will shave two inverter delays from
the DFF (perhaps more, if your clock-pair has robust drive).
Downside is, you get to build a complementary clock tree.

TINV-based DFFs (which are the norm) have built in nodes
of contention, in-the-moment. The forward and feedback
chains oppose each other until the logic state wraps back
around. You see this dealt with by making the feedback
scrawny and the forward, stout. But this could benefit from
either rebalancing, or going even further imbalanced,
depending on which transition binds you up.

You can play with "lag clocks" and "clock pullback" in trying
to design pipelined logic. For example, rather than figure a
complex carry term in one "bite" if it's wide, figure two
"precursor" terms that are right one cycle earlier, and do
the final combine ahead of the final clock so as to flatten
and use faster gates, meeting the setup in the end. This
is good for predictable things like counters; random-walk
state machines, not so much.

You can have staggered, lagged / advanced, clock branches
if you want to do the work and the work of getting the STA
to comprehend it all.
 
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    Alexxk

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