# Verilog Interview Question

1. ## Verilog Interview Question

Hi,

I was recently asked this question in a Logic Design/DV interview,

Suppose you have the following, what should be the bit width of c,d,e ? The interviewer said that the answers of my d & e were wrong. For e my answer was based on 3 as 2'b11 which would give a width of 18. What do you guys think ?

```Code Verilog - [expand]1
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// The code is my interpretation of his question.
logic [9:0] a; // can be anything, 9 & 8 were chosen as random
logic [8:0] b;
logic [?:0] c; // 17 wide ?
logic [?:0] d; // 18 wide ?
logic [?:0] e; // ??

always @(posedge clk) begin
// Assume you can finish in 1 cycle
c <= a*b; // I think c should be at least 8+9 bits wide ?
d <= a*b + 1'b1; // d should be atleast 17 (^) + 1 bits wide ?
e <= a*b + 3; // what does the 3 here mean ?
//In my 2-3 years of RTL experience I only saw people using the syntax 2'b11 or something like that.
//The interviewer was interested in what would verilog interpret the 3 as ? Is it hex by default ? 4'h3 ??
end```

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2. ## Re: Verilog Interview Question

[9:0] is 10 bits wide, i.e. 9,8,7,6,5,4,3,2,1,0 which is 10 digits.
[8:0] is 9 bits wide

a*b is 19 bits wide not 17 (9+8)

a*b +1'b1 will be 19 bits wide not 20, a*b will never be all 1's so adding a 1'b1 will never increase the result's bit width.

a*b +3 will fit in 19 bits but the result is 32-bits due to the 3 which is an integer (dependent on implementation, but is normally 32-bit)

I've been using Verilog for ~20 years, so I've probably seen + used with practically every possible thing.

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The integer math is the most annoying as it causes additional warnings in synthesis when it sees a 32-bit result being assigned to a smaller bit width variable. As long as you're willing to ignore those (I usually do) and can get through any reviews with those warnings in your synthesis report they aren't a problem.

1 members found this post helpful.

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3. ## Re: Verilog Interview Question

ads-ee answer is correct. but damn, what a weird question to ask in an interview. knowing or not knowing this doesn't make you a good designer.

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4. ## Re: Verilog Interview Question

This looks like a fine interview question. especially if the job is for an engineer that will work on porting dsp algorithms to HW. The OP just managed to hit every off-by-one error possible.

The addition of an integer literal 3 could bring up the 32b (possible) conversion, but I would expect the smaller width answer to be accepted.

A weird question would be "y <= (x + 3) >> 1;" vs "y <= (x + 2'd3) >> 1;".

5. ## Re: Verilog Interview Question

Originally Posted by ads-ee
a*b is 19 bits wide not 17 (9+8)
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Sorry about this one, I posted this question in a hurry without checking the width of a & b in code. As it's a phone interview, the question was just multiply a 9 bit register & a 8 bit register - what's the outcome. So i just remembered my answer of 17. My apologies for writing a 9 bit reg as logic [9:0] a.

Originally Posted by ads-ee
a*b +1'b1 will be 19 bits wide not 20, a*b will never be all 1's so adding a 1'b1 will never increase the result's bit width.
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Shoot, I just answered that it will overflow to 20 bits. Now I realize that unless you add (19'h111FFFF - max possible a*b) only then we overflow

Originally Posted by ads-ee
a*b +3 will fit in 19 bits but the result is 32-bits due to the 3 which is an integer (dependent on implementation, but is normally 32-bit)
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By implementation, are you talking about the environment setup

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6. ## Re: Verilog Interview Question

Originally Posted by rahdirs
By implementation, are you talking about the environment setup
software implementation of the number of bits used by a long integer. Most software implementations consider it to be 32-bits, I can't think of any simulators/synthesis tools that consider an integer in Verilog to be anything other than 32-bits, e.g. 64-bits or 128-bits. If I remember correctly the LRM states the size of an integer has to be at least 32-bits.

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