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    Converting Verilog to VHDL

    Hello,

    Is there any tool exist which convert Verilog to VHDL ?

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    Re: Converting Verilog to VHDL

    A google search would have helped you
    But why do you want to? all tools allow mixed language.



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    Re: Converting Verilog to VHDL

    I have found a working example in Verilog and I need to modify it but I need to do it in VHDL rather then Verilog.



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    Re: Converting Verilog to VHDL

    WhI checked vendor's tool are you planning to use?
    -------------
    --Akanimo.



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    Re: Converting Verilog to VHDL

    Quote Originally Posted by joniengr View Post
    I have found a working example in Verilog and I need to modify it but I need to do it in VHDL rather then Verilog.
    Why? All tools accept both languages. Maybe this gives the opportunity to learn Verilog? its not that hard to do if you understand VHDL.



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    Re: Converting Verilog to VHDL

    Quote Originally Posted by joniengr View Post
    Hello,

    Is there any tool exist which convert Verilog to VHDL ?
    Hello,

    some time ago I found "Icarus Verilog" free tool:

    http://iverilog.icarus.com/

    It basically works, but translated code is such poor - that I decided to translate code "by7 hand".

    Regards



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    Re: Converting Verilog to VHDL

    Hi again,

    I can understand the I/O Deceleration and most of the code but the code in between where signals and variable are defined is difficult in Verilog. Can someone please explain or translate into VHDL ?

    Code Verilog - [expand]
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    reg [C_AXIS_TDATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0]; 
    reg [C_AXIS_TDATA_WIDTH+2-1:0] mem_read_data_reg = {C_AXIS_TDATA_WIDTH+2{1'b0}};  
    reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; 
    wire [C_AXIS_TDATA_WIDTH+2-1:0] mem_write_data; 
     
    reg [C_AXIS_TDATA_WIDTH+2-1:0] m00_data_reg = {C_AXIS_TDATA_WIDTH+2{1'b0}};  
      
    reg m00_axis_tvalid_reg = 1'b0, m00_axis_tvalid_next; 
     
    // full when first TWO MSBs do NOT match, but rest matches 
    // (gray code equivalent of first MSB different but rest same) 
    wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && 
                 (wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && 
                 (wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0])); 
    // empty when pointers match exactly 
    wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg; 
     
    // control signals 
    reg write; 
    reg read; 
    reg store_output; 
     
    assign s00_axis_tready = ~full & ~s00_rst_sync3_reg; 
     
    assign m00_axis_tvalid = m00_axis_tvalid_reg; 
     
    assign mem_write_data = {s00_axis_tlast, s00_axis_tdata}; 
    assign {m00_axis_tlast, m00_axis_tdata} = m00_data_reg;
    Last edited by andre_teprom; 10th December 2018 at 11:47. Reason: added SYNTAX tags



  8. #8
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    Re: Converting Verilog to VHDL

    Why not find yourself a verilog tutorial?



  9. #9
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    Re: Converting Verilog to VHDL

    Code Verilog - [expand]
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    ]reg [C_AXIS_TDATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
    use signal and a std_logic_vector array type.

    Code Verilog - [expand]
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    reg [C_AXIS_TDATA_WIDTH+2-1:0] mem_read_data_reg = {C_AXIS_TDATA_WIDTH+2{1'b0}};
    mem_read_data_reg is assigned an initial value of all 0's

    Code Verilog - [expand]
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    reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
    This isn't correct, I'm suprised it compiles {} should be around the RHS stuff for concatenate.

    Code Verilog - [expand]
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    // full when first TWO MSBs do NOT match, but rest matches 
    // (gray code equivalent of first MSB different but rest same) 
    wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && 
                 (wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && 
                 (wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
    combined signal declaration of full and a continous assignment, in vhdl you will make a signal of std_logic, and then assign full with the RHS stuff.
    != is /=
    && is logic AND
    == is =

    Code Verilog - [expand]
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    assign s00_axis_tready = ~full & ~s00_rst_sync3_reg;
    ~ is NOT
    & is bit-wise AND

    Code Verilog - [expand]
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    assign m00_axis_tvalid = m00_axis_tvalid_reg;
    in VHDL
    signal m00_axis_tvalid : std_logic;
    m00_axis_tvalid <= m00_axis_tvalid_reg;


    Code Verilog - [expand]
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    assign mem_write_data = {s00_axis_tlast, s00_axis_tdata};
    { , } is & (contatenate)

    Code Verilog - [expand]
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    assign {m00_axis_tlast, m00_axis_tdata} = m00_data_reg;
    I don't think there is an equivalent in VHDL just assign the slices of m00_data_reg to the two LHS signals, you can use the 'left, 'right stuff to get the indicies to use based on the LHS signals.


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  10. #10
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    Re: Converting Verilog to VHDL

    I don't think there is an equivalent in VHDL
    Vhdl 2008 allows aggregate assignments

    (Bit1, vector2bit) <= vector3bit;



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