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    Converting Verilog to VHDL

    Hello,

    Is there any tool exist which convert Verilog to VHDL ?

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    Re: Converting Verilog to VHDL

    A google search would have helped you
    But why do you want to? all tools allow mixed language.



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    Re: Converting Verilog to VHDL

    I have found a working example in Verilog and I need to modify it but I need to do it in VHDL rather then Verilog.



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    Re: Converting Verilog to VHDL

    WhI checked vendor's tool are you planning to use?
    -------------
    --Akanimo.



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    Re: Converting Verilog to VHDL

    Quote Originally Posted by joniengr View Post
    I have found a working example in Verilog and I need to modify it but I need to do it in VHDL rather then Verilog.
    Why? All tools accept both languages. Maybe this gives the opportunity to learn Verilog? its not that hard to do if you understand VHDL.



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    Re: Converting Verilog to VHDL

    Quote Originally Posted by joniengr View Post
    Hello,

    Is there any tool exist which convert Verilog to VHDL ?
    Hello,

    some time ago I found "Icarus Verilog" free tool:

    http://iverilog.icarus.com/

    It basically works, but translated code is such poor - that I decided to translate code "by7 hand".

    Regards



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    Re: Converting Verilog to VHDL

    Hi again,

    I can understand the I/O Deceleration and most of the code but the code in between where signals and variable are defined is difficult in Verilog. Can someone please explain or translate into VHDL ?

    Code Verilog - [expand]
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    reg [C_AXIS_TDATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0]; 
    reg [C_AXIS_TDATA_WIDTH+2-1:0] mem_read_data_reg = {C_AXIS_TDATA_WIDTH+2{1'b0}};  
    reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; 
    wire [C_AXIS_TDATA_WIDTH+2-1:0] mem_write_data; 
     
    reg [C_AXIS_TDATA_WIDTH+2-1:0] m00_data_reg = {C_AXIS_TDATA_WIDTH+2{1'b0}};  
      
    reg m00_axis_tvalid_reg = 1'b0, m00_axis_tvalid_next; 
     
    // full when first TWO MSBs do NOT match, but rest matches 
    // (gray code equivalent of first MSB different but rest same) 
    wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && 
                 (wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && 
                 (wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0])); 
    // empty when pointers match exactly 
    wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg; 
     
    // control signals 
    reg write; 
    reg read; 
    reg store_output; 
     
    assign s00_axis_tready = ~full & ~s00_rst_sync3_reg; 
     
    assign m00_axis_tvalid = m00_axis_tvalid_reg; 
     
    assign mem_write_data = {s00_axis_tlast, s00_axis_tdata}; 
    assign {m00_axis_tlast, m00_axis_tdata} = m00_data_reg;
    Last edited by andre_teprom; 10th December 2018 at 11:47. Reason: added SYNTAX tags



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    Re: Converting Verilog to VHDL

    Why not find yourself a verilog tutorial?



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    Re: Converting Verilog to VHDL

    Code Verilog - [expand]
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    ]reg [C_AXIS_TDATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
    use signal and a std_logic_vector array type.

    Code Verilog - [expand]
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    reg [C_AXIS_TDATA_WIDTH+2-1:0] mem_read_data_reg = {C_AXIS_TDATA_WIDTH+2{1'b0}};
    mem_read_data_reg is assigned an initial value of all 0's

    Code Verilog - [expand]
    1
    
    reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
    This isn't correct, I'm suprised it compiles {} should be around the RHS stuff for concatenate.

    Code Verilog - [expand]
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    // full when first TWO MSBs do NOT match, but rest matches 
    // (gray code equivalent of first MSB different but rest same) 
    wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && 
                 (wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && 
                 (wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
    combined signal declaration of full and a continous assignment, in vhdl you will make a signal of std_logic, and then assign full with the RHS stuff.
    != is /=
    && is logic AND
    == is =

    Code Verilog - [expand]
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    assign s00_axis_tready = ~full & ~s00_rst_sync3_reg;
    ~ is NOT
    & is bit-wise AND

    Code Verilog - [expand]
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    assign m00_axis_tvalid = m00_axis_tvalid_reg;
    in VHDL
    signal m00_axis_tvalid : std_logic;
    m00_axis_tvalid <= m00_axis_tvalid_reg;


    Code Verilog - [expand]
    1
    
    assign mem_write_data = {s00_axis_tlast, s00_axis_tdata};
    { , } is & (contatenate)

    Code Verilog - [expand]
    1
    
    assign {m00_axis_tlast, m00_axis_tdata} = m00_data_reg;
    I don't think there is an equivalent in VHDL just assign the slices of m00_data_reg to the two LHS signals, you can use the 'left, 'right stuff to get the indicies to use based on the LHS signals.


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  10. #10
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    Re: Converting Verilog to VHDL

    I don't think there is an equivalent in VHDL
    Vhdl 2008 allows aggregate assignments

    (Bit1, vector2bit) <= vector3bit;



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    Re: Converting Verilog to VHDL

    Hi,

    Is it possible to use 'signal' in VHDL in place of 'wire' and 'reg' in Verilog ?

    The following syntax is confusing.

    parameter ADDR_WIDTH = 12,
    parameter C_AXIS_TDATA_WIDTH = 32
    reg [C_AXIS_TDATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];

    It create a reg 'mem' but the dimension 2^12 - 1 = 4096 - 1 = 4095 is not the same in LHS. Any explanation on this ?

    Why it is not written as
    reg [C_AXIS_TDATA_WIDTH+2-1:0] mem


    Also in the following. Is it defining two reg 'mem_read_data_valid_next' and 'mem_read_data_valid_reg' ? If yes then what are the dimensions of both ?
    reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
    Last edited by joniengr; 14th December 2018 at 14:53.



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    Re: Converting Verilog to VHDL

    Is it possible to use 'signal' in VHDL in place of 'wire' and 'reg' in Verilog ?
    Yes


    reg [C_AXIS_TDATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
    this is an array declaration - 4096 words (assuming ADDR_WIDTH = 12) @ (C_AXIS_TDATA_WIDTH+2) bits for each word
    equivolent to this:

    Code:
    type ram_t is array(2**ADDR_WIDTH-1 downto 0) of std_logic_vector(C_AXIS_TDATA_WIDTH+2-1 downto 0);
    signal mem : ram_t;
    You really should look into a verilog tutorial.



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    Re: Converting Verilog to VHDL

    Hi,

    I would like to include Verilog source code in VHDL testbench but I get some errors in component deceleration in VHDL testbench.

    Verilog source code

    Code Verilog - [expand]
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    module axis_fifo_v1_0 #  
    (  
        parameter ADDR_WIDTH = 12,  
        parameter C_AXIS_TDATA_WIDTH = 32  
    )  
    (  
        input  wire                   s00_axis_aclk,  
        input  wire                   s00_axis_aresetn,  
        input  wire [C_AXIS_TDATA_WIDTH-1:0]  s00_axis_tdata,  
        input  wire [(C_AXIS_TDATA_WIDTH/8)-1 : 0] s00_axis_tstrb,  
        input  wire                   s00_axis_tvalid,  
        output wire                   s00_axis_tready,  
        input  wire                   s00_axis_tlast,  
          
        input  wire                   m00_axis_aclk,  
        input  wire                   m00_axis_aresetn,  
        output wire [C_AXIS_TDATA_WIDTH-1:0]  m00_axis_tdata,  
        output wire [(C_AXIS_TDATA_WIDTH/8)-1 : 0] m00_axis_tstrb,  
        output wire                   m00_axis_tvalid,  
        input  wire                   m00_axis_tready,  
        output wire                   m00_axis_tlast  
    );


    Here is VHDL testbench

    Code Verilog - [expand]
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    entity axis_fifo_v1_0_tb is
    end axis_fifo_v1_0_tb;
     
    architecture Behavioral of axis_fifo_v1_0_tb is
     
    component axis_fifo_v1_0  
    generic(  
         ADDR_WIDTH         : integer := 12;  
         C_AXIS_TDATA_WIDTH : integer :=  32  
    );  
    port (  
        s00_axis_aclk     : in  std_logic; 
        s00_axis_aresetn  : in  std_logic;
        s00_axis_tdata    : in  std_logic_vector(C_AXIS_TDATA_WIDTH-1:0);     
        s00_axis_tstrb    : in  std_logic_vector((C_AXIS_TDATA_WIDTH/8)-1 : 0);    
        s00_axis_tvalid   : in  std_logic;   
        s00_axis_tready   : out std_logic;  
        s00_axis_tlast    : in  std_logic;   
          
        m00_axis_aclk     : in  std_logic;                   
        m00_axis_aresetn  : in  std_logic;                     
        m00_axis_tdata    : out std_logic_vector(C_AXIS_TDATA_WIDTH-1:0);   
        m00_axis_tstrb    : out std_logic_vector(C_AXIS_TDATA_WIDTH/8)-1 : 0);   
        m00_axis_tvalid   : out std_logic;                     
        m00_axis_tready   : in  std_logic;                      
        m00_axis_tlast    : out std_logic                   
    );
    end component;
     
    begin
     
    end Behavioral;
    Last edited by KlausST; 17th December 2018 at 16:41. Reason: adding code tags



  14. #14
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    Re: Converting Verilog to VHDL

    VHDL uses "downto" inplace of ":" for arrays.



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    Re: Converting Verilog to VHDL

    Hi,

    I am facing problem in converting

    Code:
     assign s00_axis_tready = ~full & ~s00_rst_sync3_reg; 
     
    assign mem_write_data = {s00_axis_tlast, s00_axis_tdata }; 
    assign {m00_axis_tlast, m00_axis_tdata} = m00_data_reg;
    in to VHDL.

    Code:
      if ( (not(full)) and (not (s00_rst_sync3_reg))) then 
      s00_axis_tready <= '1'; 
      else 
      s00_axis_tready <= '0';
      end if;
    The error I get is

    Code:
     # ** Error: E:/temp/ip_repo/hdl/AXIS_v1_0.vhd(154): Type error resolving infix expression "and" as type std.STANDARD.BOOLEAN.
    - - - Updated - - -

    Also the following I am not sure if it is correct.

    Code:
     // full when first TWO MSBs do NOT match, but rest matches 
    // (gray code equivalent of first MSB different but rest same) 
    wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && 
                 (wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && 
                 (wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0])); 
    // empty when pointers match exactly 
    wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg;

    Code:
      if ((wr_ptr_gray_reg(GC_ADDR_WIDTH) /= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH)) and 
                 (wr_ptr_gray_reg(GC_ADDR_WIDTH-1) /= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH-1)) and 
                 (wr_ptr_gray_reg(GC_ADDR_WIDTH-2 downto 0)= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH-2 downto 0))) then 
    			 
    			 full <= '1'; 
    			 else 
    			 full <= '0';
    			 end if; 
    
      if (rd_ptr_gray_reg = wr_ptr_gray_sync2_reg) then 
      empty <= '1';
      else 
      empty <= '0';
      end if;
    Can anyone please check this ?
    Last edited by joniengr; 18th December 2018 at 18:59.



  16. #16
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    Re: Converting Verilog to VHDL

    Consider that boolean and std_logic are different data types. VHDL "if" statement needs boolean expression.



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    Re: Converting Verilog to VHDL

    Hi,

    Still something is not clear. I have converted a Verilog statement to VHDL.

    Code:
    assign s00_axis_tready = ~full & ~s00_rst_sync3_reg;
    Code:
    s00_axis_tready <= not (full) and not ((s00_rst_sync3_reg));
    Is the above conversion is correct ?

    - - - Updated - - -



  18. #18
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    Re: Converting Verilog to VHDL

    Quote Originally Posted by joniengr View Post
    Hi,

    Still something is not clear. I have converted a Verilog statement to VHDL.

    Code:
    assign s00_axis_tready = ~full & ~s00_rst_sync3_reg;
    Code:
    s00_axis_tready <= not (full) and not ((s00_rst_sync3_reg));
    Is the above conversion is correct ?

    - - - Updated - - -
    A quick way to check would be to run synthesis on each of the two codes and then compare the resulting circuits in RTL viewer.
    -------------
    --Akanimo.



  19. #19
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    Re: Converting Verilog to VHDL

    The problem is that the code is big and I need to write VHDL for the whole code. I have done most of it but have some Verilog statements on which I have a doubt.

    Here is another. Can someone please look at the following conversion and also in my last post.

    Code:
    wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg;
    Code:
      if (rd_ptr_gray_reg = wr_ptr_gray_sync2_reg) then 
      empty <= '1';
      else 
      empty <= '0';
      end if;



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  20. #20
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    Re: Converting Verilog to VHDL

    Both are correct for std_logic data type. To keep the boolean expression to std_logic conversion (post #19) compact, you may use a conversion function.

    Code VHDL - [expand]
    1
    
    empty <= bool_to_std_logic(rd_ptr_gray_reg = wr_ptr_gray_sync2_reg);



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