abimann
Member level 4
How to make bram, exactly how to write depth and write width memory to make following addra addrb dina and doutb :
Code:
component bram2x80x64
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(15 downto 0);
addra: IN std_logic_VECTOR(8 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(6 downto 0);
doutb: OUT std_logic_VECTOR(63 downto 0));
end component;
component bram2x320x64
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(63 downto 0);
addra: IN std_logic_VECTOR(8 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(10 downto 0);
doutb: OUT std_logic_VECTOR(15 downto 0));
end component;
Last edited by a moderator: