Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

PLS explain how to make BRAM

Status
Not open for further replies.

abimann

Member level 4
Joined
Jun 21, 2016
Messages
77
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
673
How to make bram, exactly how to write depth and write width memory to make following addra addrb dina and doutb :

Code:
component bram2x80x64
	port (
	clka: IN std_logic;
	dina: IN std_logic_VECTOR(15 downto 0);
	addra: IN std_logic_VECTOR(8 downto 0);
	wea: IN std_logic_VECTOR(0 downto 0);
	clkb: IN std_logic;
	addrb: IN std_logic_VECTOR(6 downto 0);
	doutb: OUT std_logic_VECTOR(63 downto 0));
end component;

component bram2x320x64
	port (
	clka: IN std_logic;
	dina: IN std_logic_VECTOR(63 downto 0);
	addra: IN std_logic_VECTOR(8 downto 0);
	wea: IN std_logic_VECTOR(0 downto 0);
	clkb: IN std_logic;
	addrb: IN std_logic_VECTOR(10 downto 0);
	doutb: OUT std_logic_VECTOR(15 downto 0));
end component;
 
Last edited by a moderator:

You post makes little sense. BRAMs can either be generated as a core or infered from HDL code.
 

I think the question is based on the width difference of the ports.

The answer is the same though, use a vendor core or read the vendor docs. The vendor synthesis guide might have info on this. Although something like coregen/megafunction would be easier for a new developer working on a single design.
 

If you are using a Xilinx FPGA, read the UG901 Vivado Synthesis Guide, specially the section 'RAM HDL Coding Techniques'
 

could someone explain in two words only ?
 

Hi,

you ask for an explanation in "two words" ... but refuse to give complete informations?

..and it seems you don´t care about the already given answers.

Klaus
 

what sort of mentality is this, you were told to read the documentation like engineers do since the dawn of times. that is the right answer. don't look for shortcuts.
 

Different career.

Thats is my hobby , when i can get it easy , i try easy way. If no easy , i cannot sleep and read all docs.. In this situation i just crate it , and understand that depth is dina and doutb and , address is depends on second parameter. i changed it two or three times and understand how to do all bram configuraitons...so that is enough so now it works. Thanx to all.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top