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Vias in centre pad of PIC16F18856

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treez said:
Our contractor tells us its OK, but one of our PCB assemblers told us to have no vias there.
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I would not consider this as a general rule; the smaller the via hole diameter the less the possibility of the solder flowing to the component side of the board, causing troubles during the pick and place process. In other words, all depends on the manufacturing and assembly process as a whole, varying from case to case.
 

The bottom pad is connected to VSS so only tented or buried vias should be used unless they are all connected to another VSS point. As that is the case, I see no reason why you can't use them subject to the problems of solder flow under the package. In fact is many cases it may be the only way to connect to the center pad as tracks between other pads would have to be very thin.

Brian.
 

The question title seems to miss the problem. A low power processor probably doesn't necessarily need vias in the exposed pad, although it's surely advantageous to improve EMI behaviour. But other ICs with similar footprint are required to have vias. If it's possible with the latter, it can be done for PIC as well.

Exposed pads are usually connected by vias. You know that optimal design of vias in pad has been often discussed at Edaboard. Without repeating previous discussions and the reasoning given therein, I can tell you that I use open vias (e.g. 0.3 mm) for most designs and either simple non-conductive plugged vias or sophisticated VIPPO technology (via in pad plated over) in special cases.
 

IPC-7093
Your guide from the IPC...
Treez do you actually look at any IPC stuff regarding PCB design, manufacture and assembly?
 
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