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  1. #1
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    Difference between single flat cell check and hierarchical layout (hcell) check

    When I check LVS of a CHIP level layout with hcell, there is some sub-cell (which is defined in hcell file) is incorrect.
    But when I check it manually (single cell check), the LVS result is correct.

    Could you please let me know what is different between hcell check and single cell check. And why there are difference?
    Thank you.

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  2. #2
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    Re: Difference between single flat cell check and hierarchical layout (hcell) check

    Something from a higher level of hierarchy is stepping on
    the cell, perhaps. Have you not inspected the error for the
    cause?

    There could be other things such as settings discrepancies
    (e.g. permute rules, nets connected by label in one rules
    set and not the other, etc.). But how are we supposed to
    "let you know what is different" when you are the only one
    with the files?



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  3. #3
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    Re: Difference between single flat cell check and hierarchical layout (hcell) check

    Quote Originally Posted by dick_freebird View Post
    Something from a higher level of hierarchy is stepping on
    the cell, perhaps. Have you not inspected the error for the
    cause?
    What do you mean stepping on?
    I have inspected the error. I am sure the error is incorrect.

    Quote Originally Posted by dick_freebird View Post
    There could be other things such as settings discrepancies
    (e.g. permute rules, nets connected by label in one rules
    set and not the other, etc.). But how are we supposed to
    "let you know what is different" when you are the only one
    with the files?
    Let me make it more clear. Here is my checking story.

    The checking block is AFE. AFE has 3 different sub-block: COMP1, COMP2, LATCH.

    - When I check LVS WITHOUT hcell file for AFE. AFE is perfectly CORRECT.

    - When I check LVS WITH hcell file for AFE. AFE is INCORRECT.
    The result shown that COMP1 is INCORRECT, COMP2 is CORRECT.
    I did check COMP1 and COMP2 manually. They are perfectly CORRECT.
    Here is my hcell file
    Code:
    AFE AFE
    COMP1 COMP1
    COMP2 COMP2
    LATCH LATCH
    If there is any further information needed to provide, please let me know.



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  4. #4
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    Re: Difference between single flat cell check and hierarchical layout (hcell) check

    Sounds like it could be a port issue between COMP1 and COMP2. Probably in a symmetrical circuit that connects to both COMP1 and COMP2.



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    Re: Difference between single flat cell check and hierarchical layout (hcell) check

    Quote Originally Posted by rangermad View Post
    Sounds like it could be a port issue between COMP1 and COMP2. Probably in a symmetrical circuit that connects to both COMP1 and COMP2.
    Sorry? Could you make it more clearly? I did check for other block and it almost the same. I think it could be the problem of hierarchical check in Calibre.

    I have read the document from Mentor Calibre about hcell file but there are nothing...



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  6. #6
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    Re: Difference between single flat cell check and hierarchical layout (hcell) check

    Kind of hard to help you with the limited amount of info you posted.

    A port issue can come about by cross connecting symmetrical circuits. For example, bias1 and bias2 are currents coming from identical sized current mirrors, schematically bias1 goes to amp1, bias2 goes to amp2. If you have bias1 and bias2 swapped you will not get an error when running flat but you will get port errors when running hierarchically.

    Try removing comp1 from the HCELL list and run again. Do the same for comp2.



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