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  1. #1
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    DFT interview questions

    1. EDTbypass is passing. EDT chain patterns are failing. What could be the reasons.
    2. Two subchips are there. Shifting power is huge. HOw to reduce power dissipation?
    What are the options you have, without affecting coverage and test time? (HW or SW
    options).
    3. Setup vioations are there in your design. Which patterns would fail? (s@ or @speed?)
    4. Hold vioations are there. Which patterns would fail?
    5. Hold vioations are there. Which patterns would fail?
    6. Two flops will have the same values during shift. Whats the effect of it?
    7. Where do we use parallel testbench? Whats the use of parallel simulations?
    8. If you have simulations failures, what are the things you would look at?
    9. In synthesis, if area is not meeting the target, what would you do?
    10. If some flops in two clock domains are failing, (S@ patterns), and those failures are
    expected.HOw would you make them pass them on silicon? (no design changes are
    allowed.
    11. Atspeed coverage is always less than STUCK-at coverage. Why?
    12. P1500? are you aware of it?
    13. AND gate - optimal input pattern set to detect all S@ faults.
    14. What are EDT aborted faults?
    15. DRCs in ATPG

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  2. #2
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    Re: DFT interview questions

    Hi,

    What have you done so far?
    What are your ideas?
    What is your undestanding?

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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  3. #3
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    Re: DFT interview questions

    Quote Originally Posted by Nitin1245 View Post
    1. EDTbypass is passing. EDT chain patterns are failing. What could be the reasons.
    2. Two subchips are there. Shifting power is huge. HOw to reduce power dissipation?
    What are the options you have, without affecting coverage and test time? (HW or SW
    options).
    3. Setup vioations are there in your design. Which patterns would fail? (s@ or @speed?)
    4. Hold vioations are there. Which patterns would fail?
    5. Hold vioations are there. Which patterns would fail?
    6. Two flops will have the same values during shift. Whats the effect of it?
    7. Where do we use parallel testbench? Whats the use of parallel simulations?
    8. If you have simulations failures, what are the things you would look at?
    9. In synthesis, if area is not meeting the target, what would you do?
    10. If some flops in two clock domains are failing, (S@ patterns), and those failures are
    expected.HOw would you make them pass them on silicon? (no design changes are
    allowed.
    11. Atspeed coverage is always less than STUCK-at coverage. Why?
    12. P1500? are you aware of it?
    13. AND gate - optimal input pattern set to detect all S@ faults.
    14. What are EDT aborted faults?
    15. DRCs in ATPG
    so many mixed concepts and contexts in one post.
    Really, I am not Sam.



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  4. #4
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    Re: DFT interview questions

    Quote Originally Posted by Nitin1245 View Post
    1. EDTbypass is passing. EDT chain patterns are failing. What could be the reasons.
    2. Two subchips are there. Shifting power is huge. HOw to reduce power dissipation?
    What are the options you have, without affecting coverage and test time? (HW or SW
    options).
    3. Setup vioations are there in your design. Which patterns would fail? (s@ or @speed?)
    4. Hold vioations are there. Which patterns would fail?
    5. Hold vioations are there. Which patterns would fail?
    6. Two flops will have the same values during shift. Whats the effect of it?
    7. Where do we use parallel testbench? Whats the use of parallel simulations?
    8. If you have simulations failures, what are the things you would look at?
    9. In synthesis, if area is not meeting the target, what would you do?
    10. If some flops in two clock domains are failing, (S@ patterns), and those failures are
    expected.HOw would you make them pass them on silicon? (no design changes are
    allowed.
    11. Atspeed coverage is always less than STUCK-at coverage. Why?
    12. P1500? are you aware of it?
    13. AND gate - optimal input pattern set to detect all S@ faults.
    14. What are EDT aborted faults?
    15. DRCs in ATPG
    All about SCAN, how's about MBIST, LBIST or BSCAN ?



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