groover
Junior Member level 1
I have a module defining some memory, e.g. an array of 8-bit wide registers. These have read/write access from outside my core ("external") using a typical 8-bit-wide bus.
From inside my core ("internal") I have two modules A and B that also need read/write access, however for some registers they will need to read/write all eight bits and for others they need to read/write a single bit without affecting any other bits.
I could expose in the registers module interface every single bit for read/write but that won't be manageable in the long term as the number of registers and bits might grow over time.
I am thinking that my only option is a multi-port RAM with the following interfaces:
The bit mask would mask out any bits that should not be modified during the 8-bit write and would be put onto the internal bus by the writing module.
I could make blocks A and B share access to the RAM but then they each have to know what the other is doing which might get messy.
I am using Verilog.
Is this the usual way to solve this problem? Am I over-complicating it? Thanks!
From inside my core ("internal") I have two modules A and B that also need read/write access, however for some registers they will need to read/write all eight bits and for others they need to read/write a single bit without affecting any other bits.
I could expose in the registers module interface every single bit for read/write but that won't be manageable in the long term as the number of registers and bits might grow over time.
I am thinking that my only option is a multi-port RAM with the following interfaces:
- 8-bit read/write port 0 for external accesses
- 8-bit read/write port 1 for internal accesses from module A with an 8-bit mask for writing
- 8-bit read/write port 2 for internal accesses from module B with an 8-bit mask for writing
The bit mask would mask out any bits that should not be modified during the 8-bit write and would be put onto the internal bus by the writing module.
I could make blocks A and B share access to the RAM but then they each have to know what the other is doing which might get messy.
I am using Verilog.
Is this the usual way to solve this problem? Am I over-complicating it? Thanks!