Best Way to Implement Shared RAM

There will never be two modules that need to write the same bit at the same time (hence the merged A/B write), however one module may write it and another module may read it. This is in addition to read access via the "external" interface to my core.

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groover said:

to it to keep everything in one place.

I see that for the size of memories, the width of buses, etc. putting values in parameters allows instantiation of different copies of module with different settings, so maybe the number of registers is a special case and can be a parameter, but considering my aim of describing bits in one place how would you recommend I do this without defines?

Thanks!

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They won't need to write to the same bit at any time. For example TXBUSY would only be written by the Tx module.

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ads-ee said:

`include my_parameters_of_the_register_definitions.vhd and include it in any file that needs to access those address definitions.

or pass the parameters through the instantiations of all the modules from the top level (my preferred method).

Using parameters makes code far more portable and reusable.

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