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  1. #1
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    Using different time units in Verilog simulation

    Hello,

    In VHDL one can use different time units to schedule simulation events. For example:
    Code:
    x <= '0' , '1' after 2 ns , '0' after 4 ms ;
    From what I know for similar purposes Verilog uses the # sign followed by the number of simulation time units.
    Is there something equivalent in Verilog to my VHDL example ?

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    Re: Using different time units in Verilog simulation

    SystemVerilog allows time units.
    Code Verilog - [expand]
    1
    2
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    x <= 0;
    x <= #2ns 1;
    x <= #4ms 0;
    Dave Rich
    Senior Verification Consultant
    Mentor Graphics Corporation


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  3. #3
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    Re: Using different time units in Verilog simulation

    verilog has no equivalent that I know of. it gets ugly when folks try to do gate level simulations with multiple clocks/frequencies and no common multiplier can be applied.
    Really, I am not Sam.


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