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Using different time units in Verilog simulation

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shaiko

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Hello,

In VHDL one can use different time units to schedule simulation events. For example:
Code: 
x <= '0' , '1' after 2 [COLOR="#FF0000"]ns[/COLOR] , '0' after 4 [COLOR="#0000FF"]ms[/COLOR] ;

From what I know for similar purposes Verilog uses the # sign followed by the number of simulation time units.
Is there something equivalent in Verilog to my VHDL example ?
 

SystemVerilog allows time units.
Code Verilog - [expand]
1
2
3

x <= 0;
x <= #2ns 1;
x <= #4ms 0;
 
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    shaiko

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verilog has no equivalent that I know of. it gets ugly when folks try to do gate level simulations with multiple clocks/frequencies and no common multiplier can be applied.
 
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