jinformations
Newbie level 4
Hello,
I am a senior at Indiana State University. My major is Information Technology but I am taking a verilog class to get an intro into it. I created a full adder but I am not sure how to get it to display on a 7 segment display. I tried to do some research but the way some of the coding is confuses me.
This is what I have so far for my full adder that currently adds 3 inputs and produces a 4-bit output.
I am a senior at Indiana State University. My major is Information Technology but I am taking a verilog class to get an intro into it. I created a full adder but I am not sure how to get it to display on a 7 segment display. I tried to do some research but the way some of the coding is confuses me.
This is what I have so far for my full adder that currently adds 3 inputs and produces a 4-bit output.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 module Fulladd( input a, input b, input cin, output s, output cout ); xor(s, a, b, cin); and(t1, a, b); and(t2, a, cin); and(t3, b, cin); or(cout, t1, t2, t3); endmodule module add3(a2, a1, a0, b2, b1, b0, s2, s1, s0, cout); input a2, a1, a0, b2, b1, b0; output cout, s2, s1, s0; Fulladd stage0 (a0, b0, 0, s0, c1); Fulladd stage1 (a1, b1, c1, s1, c2); Fulladd stage2 (a2, b2, c2, s2, cout);