shaiko
Advanced Member level 5
Hello,
Are they equivalent ?
Code:
I noticed that in Verilog both of the constracts below compile correctly.
// some_parameter is used after some_input
module some_module
#(
parameter some_parameter
)
(
input some_input [ some_parameter : 0 ]
) ;
endmodule
// some_parameter is used before some_input
module some_module
#(
parameter some_parameter
)
(
input [ some_parameter : 0 ] some_input
) ;
endmodule