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  1. #1
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    Verilog & System Verilog - port sizing by inheritance

    Hello,

    VHDL supports leaving the size of component ports unconstrained during declaration.
    Unconstrained ports are constrained during elaboration by inheriting the sizes of the signals we connect to them.

    Example:
    Code:
    signal some_signal : std_logic_vector ( 7 downto 0 ) ;
    
    instantiation_of_some_entity : some_entity 
    (
      some_port => some_signal
    ) ;
    
    --some_entity could have been declared as: 
    
    entity some_entity is
    port 
    (
      some_port : std_logic_vector ( 7 downto 0 ) ; some_port is constrained
    ) ;
    end entity some_entity ;
    
    --some_entity could have also been declared as: 
    
    entity some_entity is
    port 
    (
      some_port : std_logic_vector -- some_port is unconstrained
    ) ;
    end entity some_entity ;
    Questions:
    1. Does Verilog support this?
    2. Does System Verilog support this?

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  2. #2
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    Re: Verilog & System Verilog - port sizing by inheritance

    Verilog does not support this. SystemVerilog has dynamically sized unpacked arrays, but nothing for packed arrays (vectors).

    What you can do is pass the size of a port as a module parameter, and use that parameter to size the port.
    Dave Rich
    Senior Verification Consultant
    Mentor Graphics Corporation


    1 members found this post helpful.

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