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Repeated setting default values in case statement in Verilog?

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stanford

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For example, if you want such behavior: you want a = 1, b = 0, c = 0, d = 0, when in = 0, and you want everything to = 0 if in = 1, I'm having to repeat writing a=0; b=0; c=0; d=0;. Once at the top to set them to 0 if they are not set within one of the case statements, and another in the default case statement, in case 'in' does not match any case. I'm just wondering if there is a better way to write this and avoid this duplicate default value assignment.

Code: 
always_comb
  [B]a=0;
  b=0;
  c=0;
  d=0;[/B]
  case (in)
    0: a=1;
    2: b=1;
    4: c=1;
    5: d=1;
    default: [B]a=0; b=0; c=0; d=0;[/B]
endcase
 

You should not need the default branch. All variables get assigned in all possible branches of the always_comb_block.

But if your synthesis tool has a problem with that style of coding, you can put your default values in a function

Code Verilog - [expand]
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always_comb begin
  set_defaults;
  case(in)
  ...
  default: set_defaults;
  endcase
end
function void set_defaults;
 a=0; b=0; c=0; d=0;
endfunction
 

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