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    Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

    Hi,



    I am working wothCicado 3017.3 targeting a zc706 board.



    I am trying to write some data in the DDR3 of PL and then use AXI DMA (or CDMA, I am a liitlebit confused which one) to read that data from DDR3-PL and write into a Block RAM. My design proposal is like below. I have implemented and generated bitstream.

    In this design, I write a datato DDR3-PL through PCIe and they try to transfer it to the BRAM via Zynq Processor in SDK.

    I could write data to DDR3-PL via PCIe, but when I read the content of BRAM, it is not identical with datain DDR3-PL.

    Can anyone help me to solve this issue? Thanks in advance for your support.

    Best,

    DaryonClick image for larger version. 

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  2. #2
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    Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

    I suggest to break the problem into smaller parts.
    In SDK you can find the Memory Test Application (next to Hello World app) that finds memory components in your design and performs read/write checks.

    In next step I suggest to make a connection between data stream from DDR to the data buffers inside Zynq. Then next step would be to transfer data from that buffer to the BRAM.
    To encourage me to help more, click on "Helpful Post" if you feel that I've helped you.



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    Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

    Quote Originally Posted by niciki View Post
    I suggest to break the problem into smaller parts.
    In SDK you can find the Memory Test Application (next to Hello World app) that finds memory components in your design and performs read/write checks.

    In next step I suggest to make a connection between data stream from DDR to the data buffers inside Zynq. Then next step would be to transfer data from that buffer to the BRAM.

    Thanks @Nikiki for your reply. Can you please elaborate more on this sentence : "make a connection between data stream from DDR to the data buffers inside Zynq"

    What do you mean data stream from DDR?! You know that DDR has only 1 S_AXI port which is not stream
    What do you mean by the data buffers inside Zynq? where are they and how can I enable them?

    Thanks again for your support.

    Daryon



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    Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

    When you use AXI DMA to transfer data from Zynq to DDR, then you would get: Stream (Zynq) => Memory Mapped (DDR).
    When you transfer data from DDR to Zynq, then you would get: Memory Mapped (DDR) => Stream (Zynq).

    By "data buffers" I mean e.g. BRAMs.

    The following link can be helpful:
    https://forums.xilinx.com/t5/Xcell-D...MA/ba-p/560632
    To encourage me to help more, click on "Helpful Post" if you feel that I've helped you.



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    Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

    I have implemented and generated bitstream.
    Do you have a test-bench for your design?
    Even if the design is complex, I would suggest you to build one.
    Many design bugs are caught and debugging becomes easier on complete simulation.
    FPGA enthusiast!



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