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    Antenna Protection between Diode Cell and Well ring.

    In order to prevent atenna effect, there are 4 methods which I know.

    1. Metal jumper
    2. Poly gate area modification
    3. Add diode cell protection. (N+/PW for NMOS; P+/NW for PMOS)
    4. Add well ring to create junction like diode protection. (Nwell ring for NMOS, Pwell ring for PMOS)

    In the method 3, 4, could you tell me what is different between them? Thank you very much.

    I see in some cases, designer decides to add a diode cell instead of drawing a well ring.

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    Re: Antenna Protection between Diode Cell and Well ring.

    Quote Originally Posted by quyleanh View Post
    ...
    3. Add diode cell protection. (N+/PW for NMOS; P+/NW for PMOS)
    4. Add well ring to create junction like diode protection. (Nwell ring for NMOS, Pwell ring for PMOS)

    In the method 3, 4, could you tell me what is different between them? Thank you very much.

    I see in some cases, designer decides to add a diode cell instead of drawing a well ring.
    Adding a diode close to the gate surely is the safest method against the antenna effect jeopardy - particularly if there is no direct M1 connection from a driver (which always has a diode connection to its substrate) to the gate.

    In any case, a single diode to substrate is sufficient - substrate here meaning the real p-substrate for NMOS, respectively the n-substrate of an n-well for PMOS, i.e. an N+/p - diode to protect an NMOS gate, and a P+/n-well - diode for a PMOS gate.


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  3. #3
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    Re: Antenna Protection between Diode Cell and Well ring.

    Quote Originally Posted by erikl View Post
    Adding a diode close to the gate surely is the safest method against the antenna effect jeopardy - particularly if there is no direct M1 connection from a driver (which always has a diode connection to its substrate) to the gate.
    Could you please let me know why we have to connect METAL1 directly from gate (of Diffirential Pair for example) to the Diode?
    Why we cannot VIA up to MET2 and then connect?

    Quote Originally Posted by erikl View Post
    In any case, a single diode to substrate is sufficient - substrate here meaning the real p-substrate for NMOS, respectively the n-substrate of an n-well for PMOS, i.e. an N+/p - diode to protect an NMOS gate, and a P+/n-well - diode for a PMOS gate.
    So the diode region, which is fromed from well ring and substrate, is not sufficient? Like I put N-well ring near NMOS in Psubstrate, it isn't good?



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    Re: Antenna Protection between Diode Cell and Well ring.

    Quote Originally Posted by quyleanh View Post
    Could you please let me know why we have to connect METAL1 directly from gate (of Diffirential Pair for example) to the Diode?
    Why we cannot VIA up to MET2 and then connect?
    Yes, you can. But you should take care that the M1 connection wire to the V12 via isn't too long, otherwise you'd risk an antenna violation error at the M1-only ARC.

    Quote Originally Posted by quyleanh View Post
    So the diode region, which is fromed from well ring and substrate, is not sufficient? Like I put N-well ring near NMOS in Psubstrate, it isn't good?
    I'm not sure if I understand you correctly: you think of an N-well ring around the NMOS whose gate you want to protect? Of course this works well. However such a ring would add a lot of capacitance to the gate. A small N+ on N diode area in the Psubstrate near the NMOS would be sufficient to protect its gate, connected by M1 (or M1-M2-M1, if need be).


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    Re: Antenna Protection between Diode Cell and Well ring.

    Quote Originally Posted by erikl View Post
    Yes, you can. But you should take care that the M1 connection wire to the V12 via isn't too long, otherwise you'd risk an antenna violation error at the M1-only ARC.
    Sure, I have to make sure the METAL1 is not too long in oder to prevent error. Just because I heard about "only" METAL1 is allowed to connect between diode and protected gate. (maybe I have mistaken).

    Quote Originally Posted by erikl View Post
    I'm not sure if I understand you correctly: you think of an N-well ring around the NMOS whose gate you want to protect? Of course this works well. However such a ring would add a lot of capacitance to the gate. A small N+ on N diode area in the Psubstrate near the NMOS would be sufficient to protect its gate, connected by M1 (or M1-M2-M1, if need be).
    Yes. Now I understand your point. Thank you very much for your kind support.



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