EceWoman
Newbie level 3
Hello,
I am a total noob in VHDL/Verilog so I ll need your valuable help. I am trying to design a 2x2 ethernet switch like this : https://github.com/kc285/ethernet/tree/master/SystemVerilogReference/projects/ethernet
I have only one clock clk, and I want to have a syncrhonous start of packet A signal (in_sopA) so in the testbench i write
inside the design I have written
so i notice that write_en_A is asserted after 2 clock cycles and not during the current posedge of the clk. So I believe there is a problem tracing posedge of in_sopA because posedge of in_sopA is happening nearly the same time with if1.clk posedge. Should I add another clock and generate in_sopA with the second clock?
i tried changing the sensitivity list to
end it works fine.
2nd question ,
can you please guide me how would you try to design a 2x2 switch ? Your first thoughts of the overall architecture
3rd, can you give me some general guidelines of when one should use FSM in a design?
Thank you very much, I would kindly ask you, if you have the kindness to answer my questions to be as illustrative as you can.
Thank you again
I am a total noob in VHDL/Verilog so I ll need your valuable help. I am trying to design a 2x2 ethernet switch like this : https://github.com/kc285/ethernet/tree/master/SystemVerilogReference/projects/ethernet
I have only one clock clk, and I want to have a syncrhonous start of packet A signal (in_sopA) so in the testbench i write
Code:
@(posedge if1.clk);
if1.in_sopA <= 1'b1;
inside the design I have written
Code:
always @(posedge if1.clk) begin
if (in_sopA == 1'b1 && full_A == 1'b0) begin
write_en_A <= 1'b1;
fifo_a_dest_addr <= inDataA;
end
end
so i notice that write_en_A is asserted after 2 clock cycles and not during the current posedge of the clk. So I believe there is a problem tracing posedge of in_sopA because posedge of in_sopA is happening nearly the same time with if1.clk posedge. Should I add another clock and generate in_sopA with the second clock?
i tried changing the sensitivity list to
Code:
always @(in_sopA) begin
if (in_sopA == 1'b1 && full_A == 1'b0) begin
write_en_A <= 1'b1;
fifo_a_dest_addr <= inDataA;
end
end
end it works fine.
2nd question ,
can you please guide me how would you try to design a 2x2 switch ? Your first thoughts of the overall architecture
3rd, can you give me some general guidelines of when one should use FSM in a design?
Thank you very much, I would kindly ask you, if you have the kindness to answer my questions to be as illustrative as you can.
Thank you again