Shorted ground ports in Layout

Hello.
I faced some problem with ground ports. In layout I have ground plate (M9) , that has several ground ports. LVS sees all these ports as shorted. For inductors , I use metal resistor in order to separate port's conflict , but it is very difficult to use resistors for ground solid plate...

This (IME) depends on how the netlister and ERC respond to
duplicate ports.

One thing that has worked when multiple same-named ports
are shorted for cause (by design) and the tool complains,
is to take the port labels off all but one (replace w/ plain
text, for documentation purposes).

But check the ERC settings, you may be able to suppress
shorts warnings (which, if thrown on features which are
obviously the same net and the same port name, means
the tool is not getting it) either globally or specifically

Another option, if the tool comprehends resistance and
does so using a marker polygon, is to impose trivial-L /
trivial-R regions between the pad and the plane, and
name the GND pads to (say) GND1, GND2, GND3... and
let the netlist think the milliohms are on purpose (if you
care about simulation, make the schematic represent
the real pad-plane L, R). You might have to alter how
you lay out the pads (like, relieve the corners and make
current flow orthogonally outward from the pad only on
the three sides, through three resistor-polygons in parallel,
represented to suit).

If you use Assura, there should be an option which has been developed by PDK author to solve these kind of problems.

I use Calibre.
I try to use metal resistors , but it is very difficult with complicated polygons.

Yakov_Yakov said:

I use Calibre.
I try to use metal resistors , but it is very difficult with complicated polygons.

Click to expand...

There should be an option to hide ( or to fake ) these structures while LVS is running.

You do not have to use metal resistors or use different port names for multiple pads/ports on power/ground nets.

In LVS, and/or in extraction, there should be a setting that would tell the tool/flow whether to short the ports with the same names, or keep them.
For example, if your label for ports/pads is VSS, and you have many of them, the LVS would name them using unique suffixes, e.g. VSS_1, VSS_2, etc.

For IR/EM analysis of power / ground nets, you should keep all pads/ports as unique, i.e. not shorting them (unless you can safely assume that the shorting will be done at the upper hierarchy levl, using low-resistive metals).