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  1. #1
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    clocking issues in capturing debug signals in ILA

    Hi All,

    i have a design which has 125Mhz Ip clk coming from onboard oscillator.

    I then generated many frequencies(div2,div4 etc) using MMCM_ADV for different modules.
    Now i wanna probe the signals in each module and see them in logic analyzer.

    But tool is throwing error like the clock for debug_hub is not a free running.

    so is it like each and every ILA needs clock coming from onboard osc ?
    But its frequency is diff then the frequency of signals i probed as they wer running on MMCM generated clocks.

    How can i probe those signals? what are some standard industrially accepted strategies ?

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  2. #2
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    Re: clocking issues in capturing debug signals in ILA

    Now i wanna probe the signals in each module and see them in logic analyzer.
    Please post a screenshot of your ILA connection/s to the modules.

    Now i wanna probe the signals in each module and see them in logic analyzer.
    What is the nature of signals you want to probe?

    so is it like each and every ILA needs clock coming from onboard osc ?
    Not at all. It can be the clock signal fed into your module.

    Are you planning to probe the clocks?
    If yes, that cannot happen. Any other signal you can probe.

    Shown below is an inst of an ILA core in VHDL. Note the clock connection and the signals to be probed connections.
    Code:
            ila_inst: ila_module
            port map(
                clk        => ffm_clk_i,             <--- clock only connected here
                probe0(0)  => ff_fifo_full, 
                probe1(0)  => ff_fifo_wr_en, 
                probe2(0)  => ff_fifo_empty,  
                probe3(0)  => ff_fifo_rd_en,
                --
                probe4(0)  => eof, 
                probe5(0)  => forward_enable,  
                probe6     => cmp_reg(0), 
                probe7     => cmp_reg(1), 
                probe8     => cmp_reg(2),          
                probe9(0)  => drainer_fifo_wr_en  
            );
    Last edited by dpaul; 15th November 2018 at 09:59.
    FPGA enthusiast!


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  3. #3
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    Re: clocking issues in capturing debug signals in ILA

    Group every probed signal based on its clock domain. Use as many ILAs as you have clock domains i.e. connect the probed signals and clock from one clock domain to one ILA.
    To encourage me to help more, click on "Helpful Post" if you feel that I've helped you.



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  4. #4
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    Re: clocking issues in capturing debug signals in ILA

    thanks to you all..
    I figured out the problem. I had the reset pin connected to MMCM so the output clock from MMCM was not free running.
    After i removed it , its working fine.



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