Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
closing time in rc is trivial, it either passes or it needs a redesign. people won't even call it timing closure because it really isn't. either you meet specs or go home.
on the physical synthesis side of things, you have to understand what are the sources of issues. clock is not ideal, power distribution is not ideal, coupling hurts you, routing is extracted instead of estimated, etc. there is no one size fits all solution to closure. just tackle one problem at a time. fanout control is really not an issue/solution.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
