Ringing between pads and digital inputs?

Hi fellow engineers!
I am doing a digital block for a mixed signal ASIC as part of my diploma thesis. I allready finished the digital design (with genus and innovus) and have it imported into virtuoso. Everything works fine up to the point where I have the post layout simulation of the finished asic with pads and simulate the design with 1nH inductances at each pad (simulating the bonding wires).
When I have the bonding wire inductance in series with the gate capacitance of some standard cells, I get a very strong ringing (when applying a clock transition on that input of the asic) on that line. Adding a serial resistor of 400Ohm/(Number of connected gates) dampens this ringing enough. Without the resistor there is a 800mV peak peak ringing on my 1.8V logic inputs.
Is this normal behavior? I simulate the digital input cells alone and it seems they allready have a 1kOhm input resistor.

Those simulations were done post-layout in Virtuso.

Thank you for your help!

Is this normal behavior?

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Definitely yes. Ground wire inductance may be even more problematic, creating coupling between in- and output signals ("ground bounce").

Did you use realistic signal rise time in your simulation?

I allready encountered that ground bounce phenomenon, after powerup the onchip ground jumps to about -800mV and needs about 50ns to stabilize at 0V.
I used 100ps as rise time, I think this will be realistic for signals coming from an 1GHz Labview PXI digital measurement system.

So if this is the normal behaviour, how is it normaly solved? Adding that gate resistor (is there a recommended size?)? Or is there a better option? Sadly there are no courses on digital chip design at my university, I am working with the analog circuit design department and the know how on digital integrated circuits is very limited.

Thank you a lot!

How can the inductor be in series with any standard cell? Your pads should never allow this.

Emulating the bond wires as simple gross lumps contributes
to the ringing, making it lower frequency and higher amplitude.
Mutual L, C coupling is also probably ignored. But none of
this lies between pads and core ("cells"), rather between
package leads and the chip pads. The bounce will not make
it past the input buffer front end. But the ground inductance
makes the chip ground move w.r.t. the simulation GND and
this contaminates all chip signals unless you probe them
differentially w.r.t. the chip ground reference instead (may
have to use a bunch of vcvs-es to create the differential
voltages, to plot).