Alexxk
Junior Member level 3
Hi fellow engineers!
I am doing a digital block for a mixed signal ASIC as part of my diploma thesis. I allready finished the digital design (with genus and innovus) and have it imported into virtuoso. Everything works fine up to the point where I have the post layout simulation of the finished asic with pads and simulate the design with 1nH inductances at each pad (simulating the bonding wires).
When I have the bonding wire inductance in series with the gate capacitance of some standard cells, I get a very strong ringing (when applying a clock transition on that input of the asic) on that line. Adding a serial resistor of 400Ohm/(Number of connected gates) dampens this ringing enough. Without the resistor there is a 800mV peak peak ringing on my 1.8V logic inputs.
Is this normal behavior? I simulate the digital input cells alone and it seems they allready have a 1kOhm input resistor.
Those simulations were done post-layout in Virtuso.
Thank you for your help!
I am doing a digital block for a mixed signal ASIC as part of my diploma thesis. I allready finished the digital design (with genus and innovus) and have it imported into virtuoso. Everything works fine up to the point where I have the post layout simulation of the finished asic with pads and simulate the design with 1nH inductances at each pad (simulating the bonding wires).
When I have the bonding wire inductance in series with the gate capacitance of some standard cells, I get a very strong ringing (when applying a clock transition on that input of the asic) on that line. Adding a serial resistor of 400Ohm/(Number of connected gates) dampens this ringing enough. Without the resistor there is a 800mV peak peak ringing on my 1.8V logic inputs.
Is this normal behavior? I simulate the digital input cells alone and it seems they allready have a 1kOhm input resistor.
Those simulations were done post-layout in Virtuso.
Thank you for your help!