Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

really need help about ENOB simulation and improvement

Status
Not open for further replies.

usernamer

Newbie level 6
Joined
Oct 26, 2018
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
200
Hi all,
I have some questions about ENOB measurement and improvement, I know it is a long post and many questions but I do not have an idea how to go on, I would be really grateful if someone could answer even to only a part of the questions.
I have to design a 9 bit accuracy amplifier with a gain of 2 for an ADC, and supply voltage is 800 mV.
The closed loop amplifier is a capacitive reset switched capacitor gain circuit, where clock frequency is 100 MHz so the only instant of the output waveform that matters is the one right before the amplification phase ends. See figure
capres.jpg
only difference is that I am using a fully differential version of it.
The amplifier is a two stage folded cascode.

For the simulation I am using spectrum in Cadence virtuoso, which calculates automatically ENOB and SINAD. So I would need to get ENOB=9 and the way I use DFT is as follows:
My differential input signal is a sinusoid at f=50 MHz, and my DFT takes samples at F=2f=100 MHz at the end of each amplification phase (this is the way the following stage is supposed to behave) and the interval of the DFT is an integer number of periods of my input signal.
In the figure below the markers show 2 of the points where I am sampling right before the reset phase (red output, yellow input differential signals)
sketch.jpg
Also I am using strobeperiod to have uniform raw data points.

Here come some of my doubts:
  1. first not only the ENOB I get is lower than 9 but it also depends on the initial phase of my input sinusoid, so it is higher if the sampling occurs at the peaks of the waveform, why is that?
  2. It also depends on the frequency of input signal (I do not understand why since for each input signal anyway has a frequency equal or less than half of the sampling frequency so the DFT should "see" the correct signal regardless of its frequency). Again why does this happen? My hypothesis: it is because at 50MHz DFT does not "see" the higher harmonics (odd multiples) due to distortion, becuase it is sampling at 100 MHz, is it this the reason?
  3. I know that one should choose a number of samples N=2^n (a power of 2) so the algorithm is faster, but it is still correct even though I do not choose a power of two, isn't it? It should just be slower?
  4. I get the following warning: "The function values at from and to are not equal." but since the waveform is noisy I suppose it is not possible that first and last values are equal, is there a way to fix this warning?

Also as far as I know, the only ways now to improve ENOB would be to reduce noise or distortion:
  1. To reduce noise which has root mean square vn, in the feedback amplfier I have vn^2=γkT/C (where C=load capacitance and γ a constant parameter) so I cannot do much if I cannot increase C, is it correct?
  2. To reduce distortion I should improve linearity so I could inject higher signals and thus get better SINAD, but how can this be done? Or where could I find such information?

Thanks for helping
 

I don't understand your issues exactly, so I am not sure my answers are correct:
1. if fin=50MHz, fsampling=100MHz and you take samples from the input signal at every zero crossing it is not a surprise the ENOB is smaller. All of your samples are zeros, data doesn't represent a signal, just noise
2. from similar to previous reason it can happen you sample the same value points of a signal, and data won't represent the real signal when the fsampling is integer multiple of fin.
3. pass, but choose power of 2
4. just a guess, but are you simulating transient or PSS analysis? PSS is used when the fsampling is integer multiple of fin.

1. it is a bit simplified equation for the ... output noise maybe. It is true for an RC... but flicker or thermal noise is the problem? Where is this load capacitor exactly?
2. pass. I should see your whole circuit, I don't know.
 
Hi,

for 50MHz signal you can´t use 100MHz sampling frequency.

Nyquist says HIGHER than twice the signal frequency.

The problem is: Theoretically you may continously sample the zero crossings (= 0V) of the 50MHz .. but maybe you sample the peaks of the 50MHz or anything inbetween. But you can´t know what you are sampling.

And when you try to sample 50MHz with 101MHz (whis is within Nyquist) you need a window size of 5050 samples.. to get full information.

Note: Nyquist gives the limit - this does not mean that it is useful to go (close) to the limit.

Klaus
 
Thanks a lot for your answers, I will try to be more clear regarding my questions

2. from similar to previous reason it can happen you sample the same value points of a signal, and data won't represent the real signal when the fsampling is integer multiple of fin.
Why if fsampling is integer multiple of fin data won't represent the signal? Where can I read something about this? As far as I know from Nyquist-Shannon sampling theorem it is not excluded that sampling frequency could be an integer multiple of the signal.
Anyway I have tried simulating with fin=40 MHz so that fsampling=100 MHz is not its integer multiple (I cannot take a number of samples which is a power of 2 in this case though since fsampling/fin is not a power of 2) and ENOB decreases but now I get SINAD < SNR thus I guess the DFT is "seeing" the distortion, so I guess distortion should be the main contribution to focus on to improve ENOB.
(SINAD 32dB SNR 48dB so distortion dominates)
plot.jpg

4. just a guess, but are you simulating transient or PSS analysis? PSS is used when the fsampling is integer multiple of fin.
I am simulating transient noise analysis with Noise fmax=5*amplifier bandwidth

1. it is a bit simplified equation for the ... output noise maybe. It is true for an RC... but flicker or thermal noise is the problem? Where is this load capacitor exactly?
This load capacitance is just the capacitance seen at the output of the amplifier during the amplification phase, see figure below (only difference is mine is a fully differential implementation):
brom.jpg

2. pass. I should see your whole circuit, I don't know.
The amplifier is a 2 stage folded cascode in figure below (260 MHz bandwidth, DC gain 74 dB, Vdd=800 mV)
amp.jpg
closed loop it is as follows (C1=2C2 so gain is 2):
close.jpg

In the simulations I have made until now, vin (differential input amplitude) =300 mV (over this value the amplifier doesn't show 9 bit accuracy anymore to a noiseless step voltage)
 

For the simulation I am using spectrum in Cadence virtuoso,
Use correct terminology.
Such simulator never exist.

1. first not only the ENOB I get is lower than 9 but it also depends on the initial phase of my input sinusoid,
so it is higher if the sampling occurs at the peaks of the waveform, why is that?
It is very natural, since there are only two points during one period.

2. It also depends on the frequency of input signal (I do not understand why since for each input signal anyway has a frequency equal or less than half of the sampling frequency so the DFT should "see" the correct signal regardless of its frequency).
(1) fin=50MHz, fs=100MHz
(2) fin=100MHz, fs=200MHz

Generally, (2) results in bad ENOB.

3. I know that one should choose a number of samples N=2^n (a power of 2) so the algorithm is faster,
but it is still correct even though I do not choose a power of two, isn't it?
It should just be slower?
I can not understand what you want to mean at all.
Describe correctly.

4. I get the following warning: "The function values at from and to are not equal." but since the waveform is noisy I suppose it is not possible that first and last values are equal, is there a way to fix this warning?
Simply, your simulation can not reach to steady state.

Also as far as I know, the only ways now to improve ENOB would be to reduce noise or distortion:
Can you understand your EDA Tool Play correctly ?
Do you invoke Transient-Noise Analysis ?
If not, device noises are never reflected in your EDA Tool Play.

1. To reduce noise which has root mean square vn, in the feedback amplfier I have vn^2=γkT/C (where C=load capacitance and γ a constant parameter) so I cannot do much if I cannot increase C, is it correct?
Correct.
However, most important issue is that large C require high bandwidth.
And slew rate will be slow. It results in bad ENOB.

2. To reduce distortion I should improve linearity so I could inject higher signals and thus get better SINAD, but how can this be done?
Apply large supply voltage.
Increase bias current of device to improve linearity.
If you don't care noise, use resitive feedback or degeneration.
 
Use correct terminology. Such simulator never exist.
With spectrum I was not meaning the simulator (which is instead spectre) but the tool used to get DFT in ADEL (measurements menu> spectrum)
I am using the following version of cadence virtuoso:
virtuoso version.jpg


(1) fin=50MHz, fs=100MHz
(2) fin=100MHz, fs=200MHz

Generally, (2) results in bad ENOB.
(1) also or not? If not what is the differnce between (1) and (2)?

I can not understand what you want to mean at all.
Describe correctly.
When using a DFT one has to choose how many samples to use, and usually it is suggested to use an integer number N which is a power of 2, I was just asking if still the result is correct if N is not a power of 2.

Can you understand your EDA Tool Play correctly ?
Do you invoke Transient-Noise Analysis ?
If not, device noises are never reflected in your EDA Tool Play.
Sorry I am quite new with using the simulator what do you mean by EDA tool play?
Anyway yes I have activated transient noise analysis with noise fmax=5*amplifier bandwidth

Apply large supply voltage.
Increase bias current of device to improve linearity.
If you don't care noise, use resitive feedback or degeneration.
My supply voltage is 800 mV and cannot be increased.
What do you mean by resistive feedback? I cannot place resistors in my feedback since I must use switched capacitor implementation.
If I use degeneration won't I reduce the swing resulting thus in higher distortion when my output signal is large? (purpose of improving linearity would be to be able to have wider swing at output to increase signal power in the SINAD ratio)
 

With spectrum I was not meaning the simulator (which is instead spectre)
but the tool used to get DFT in ADEL (measurements menu> spectrum)
I got you mean spectrum() function of Cadence Skill Language.

Why if fsampling is integer multiple of fin data won't represent the signal?
Where can I read something about this?
As far as I know from Nyquist-Shannon sampling theorem it is not excluded that sampling frequency could be an integer multiple of the signal.
You can not understand sampling theorem and fourier series correctly.

For fs <= 2*fin, aliasing of spectrum ocuurs.
Here spectrum is a complex number.
Phase of negative and positive spectrum are different.
Consider result of postive spectrum + negative spectrum.

Anyway I have tried simulating with fin=40 MHz so that fsampling=100 MHz is not its integer multiple
No.
fs=2*fin is not appropriate. That's all.

I recommend fs=4*fin or 8*fin or 16*fin.

Anyway yes I have activated transient noise analysis with noise fmax=5*amplifier bandwidth
Ok.
Use window for FFT, e.g. Hanning Window.

(I cannot take a number of samples which is a power of 2 in this case though since fsampling/fin is not a power of 2) and ENOB decreases
but now I get SINAD < SNR thus I guess the DFT is "seeing" the distortion,
so I guess distortion should be the main contribution to focus on to improve ENOB.
I can not judge.
What is 19.5MHz spectrum ?
fin=40MHz, Hiowever I don't know clock frequency for SC-Amplifier.
Clock frequency has no direct relation with fs of dft().

Reevaluate by setting followings.
I assume you use Cadence Spectre.

Transient Analysis Option:maxstep=1/(2*8*fin), strobeperiod=1/(8*fin), errpreset=conservative
Start=0.0 Stop=10/fin+8192/(8*fin)

Spectre Option:++aps

DFT Start=10/fin
DFT Stop=10/fin+8192/(8*fin)
DFT Sample Numbers=8192

(1) Transient Analysis without Noise
(2) Transient Analysis with Noise

Compare SINAD, SNR for both cases.

(1) also or not? If not what is the differnce between (1) and (2)?
I can not understand what you want to mean at all.
Describe correctly.

I was just asking if still the result is correct if N is not a power of 2.
Correct.
However interpolate errors are introduced for spectrum.

For N is not power of 2, dft() of Cadence Skill interpolates data and resample with power of 2 samples.
 
Last edited:

Why if fsampling is integer multiple of fin data won't represent the signal? Where can I read something about this? As far as I know from Nyquist-Shannon sampling theorem it is not excluded that sampling frequency could be an integer multiple of the signal.
Sorry, I didn't think enough on it, actually it is not a problem if sampling frequency is integer number multiple of the input frequency, only the fsampling=2*finput is the problem. My mistake.
In your circuit I assume the biggest noise contributor is the OPAmp, and to reduce noise I think not the only option to reduce the noise bandwidth by increasing the C.
To reduce flicker-noise you should try to increase diff-pair area, use PMOS differential pair instead of NMOS, you still didn't say flicker is the problem. For a switched circuit maybe not.
If the thermal noise is high you should increase the current consumption, increase Gm of the diff-pair, decrease Gm of the loads.
To improve the linearity better to increase the output headroom, optimize the common-mode level of your amplifier, and a final option to reduce the gain of the 1st stage, and add digital gain after the ADC, but last will decrease the noise performance of your system.
 

Reevaluate by setting followings.
I assume you use Cadence Spectre.

Transient Analysis Option:maxstep=1/(2*8*fin), strobeperiod=1/(8*fin), errpreset=conservative
Start=0.0 Stop=10/fin+8192/(8*fin)

Spectre Option:++aps

DFT Start=10/fin
DFT Stop=10/fin+8192/(8*fin)
DFT Sample Numbers=8192

(1) Transient Analysis without Noise
(2) Transient Analysis with Noise

Compare SINAD, SNR for both cases.

So here I tried what you said, fs=8fin, fin=12.5MHz fs=100MHz, output sinusoid amplitude is (ideally should be) 400mV (800 mV pk to pk):
first noiseless trace
noiseless trace.jpg
results that even without noise I have ENOB=8.3 while I would need 9

the noisy trace is:
noisy trace.jpg
SINAD decreases of 6dB thus looks like distortion and noise give an equal contribution.

In case it could be useful I show also the sketch in time domain:
red is the differential output waveform
orange is clock phase phi1 (amplification phase). During the other phase amplifier just holds the last voltage.
blue is the positive output voltage
green is the output of the common mode feedback (cmfb_gates in the schematic I uploaded in previous post)
time waveform.jpg

In the DFT I skipped the first 500ns because there is some transient time before the output common voltage gets stable around its 400 mV DC value


So what I wonder is, since I am taking my samples only during end of phi1 clock phase, I never sample when the circuit is on hold mode, thus I shouldn't get distortion due to hold operation, is this idea correct?
If so means that all that huge distortion is due to amplifier non linearities?
Thanks a lot for helping

- - - Updated - - -

To reduce flicker-noise you should try to increase diff-pair area, use PMOS differential pair instead of NMOS, you still didn't say flicker is the problem. For a switched circuit maybe not.
I am not sure whether flicker noise dominates, I am trying to google which kind of simulation I should do to figure it out, do you perhaps have any suggestion about it?
thank a lot
 

Hi,

did you use some analog antialias filter?
If not then please do a new measurement with filter.

The problem without filter:
One can expect mainly uneven overtones. 3x, 5x, 7x, 9x, 11x ... of the fundamental.

In your spectrum you see:
* fundamental (12,5MHz)
* 3rd overtone (37.5MHz)

if there are other overtones then they become alias frequencies:
* 5th --> 3rd
* 7th --> fundamental
* 9th --> fundamental
* 11th --> 3rd
...
but I assume the amplitude of the 5th overtone and the 11th overtone will be added to the 3rd overtone directly (without square and root..)
This may influence the ENOB value.

But to be true: I´m not sure about it.

Klaus
 
I didn't simulate SC circuits too much and I don't know how your circuit handles in-band noise of the OPAmp. If you mix it up to 2*fs before amplification probably flicker shouldn't dominate, but I am not sure you are doing this at now. But with periodic noise analysis you could figure it out, because after the simulation you can plot the noise contributors into a table, where next to the devices it is marked that what kind of noise it generates and how much percent is the contribution to the output noise. PNOISE analysis, unlike conventional noise analysis, computes frequency convention effects, noise folding, aliasing.
If fs=8*fin use PSS(Periodic Steady State) analysis, then you can add the PNOISE easily. And PSS gives much more accurate results for the fourier transform, even it does the frequency domain analysis automatically.
Setting: https://www2.ece.ohio-state.edu/~bibyk/ece822/SpectreRF_0728.pdf
 
Last edited:
If fs=8*fin use PSS(Periodic Steady State) analysis, then you can add the PNOISE easily. And PSS gives much more accurate results for the fourier transform, even it does the frequency domain analysis automatically.
Setting: https://www2.ece.ohio-state.edu/~bibyk/ece822/SpectreRF_0728.pdf
It looks a lot to read, I will start to study it and then will come back to say whether that gives some improvement to my simulation or not, thanks!

Hi,

did you use some analog antialias filter?
If not then please do a new measurement with filter.

Klaus

No I am not using such filter, should I just put an ideal low pass filter at the output of my amplifier or is there any more proper way to do this?
 

No I am not using such filter,
should I just put an ideal low pass filter at the output of my amplifier
I don't think LPF at output is required, since your target SNR is 56dB at most.

or is there any more proper way to do this?
However, if you would like to place LPF at output, use "analogLib/vcvs of gain=2", "analogLib/res as terminator", "rfLib/butterworth_lp of fc=fs/4" and "analogLib/res as load".

first noiseless trace
results that even without noise I have ENOB=8.3 while I would need 9
SINAD=51.7dB, SNR=156.6dB
If so means that all that huge distortion is due to amplifier non linearities?
I think so.

So what I wonder is,
since I am taking my samples only during end of phi1 clock phase,
I never sample when the circuit is on hold mode,
thus I shouldn't get distortion due to hold operation,
is this idea correct?
Correct.

Can you undetstand what causes SNR degradation in SC-Amplifier ?

(1) Device Noise, e.g. thermal, flicker noise
(2) Harmonic Distortion
(3) Clock feedthrough
(4) Glitch noise
(5) Droop of hold waveform
(6) Ringing of hold waveform, Overshoot, Undershoot, etc.
(7) Sampling Jitter
(8) Bandwidth limit of sampling
etc....

Sampling frequecny of dft(), fs has to be larger than clock frequency of SC-Amplifier, fclk.
However you set fclk=fs=100MHz.

If you choose sampling point at center or a slightly later for edge of hold period, it will give you best SINAD, since you have only one sample for one hold period.

Maybe your sampling point is just edge of hold period, it will cause SNR degradation.
However it is small degradation compared to 3rd-order harmonics.

If you would like to include all degradations, set "fclk=8*fin, fs=8*fclk" and "maxstep=1/(2*fs), strobeperiod=1/fs" for Transient Analysis.

Or invoke Shooting-Newton-PSS Analysis of fundamental_frequency=fin.

I am not sure whether flicker noise dominates,
I am trying to google which kind of simulation I should do to figure it out,
do you perhaps have any suggestion about it?
I don't think flicker noise is dominant.

Try invoke noise contribution analysis.

You can do it by PSS/Pnoise or Transient Noise Analysis.

You can set "noiseoff" and "noiseon" in Transient Noise Analysis.

Code:
//+   noiseoff=[ R1p R1m R2p R2m R3p R3m R4p R4m ]
//+   noiseon=[ I0.I0.R0 I0.I0.R1 ]
//+   noiseon=[ I0.I0.R0 I0.I0.R1 I0.I0.IDAC1 I0.I0.I1 ]

Noise of PSS/Pnoise is no more than small signal analysis.
https://www.designers-guide.org/Forum/YaBB.pl?num=1258339986/#13
 
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top