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    Tracking 'X' in the gate lavel simulation

    I am trying to fix my design, it works in the ModelSim but doesn't work in the hardware. I ran gate level simulation (with the same test bench) but shortly after starting some debug at the output of the FPGA signals got 'X'. Is there any way to track where and when 'X' appears inside the design? All input data from memory are defined. I have an access to some Mentor's tools (QuestaSim, Precision Synthesis etc).

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    Re: Tracking 'X' in the gate lavel simulation

    Did you try Modelsim TraceX function?



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    Re: Tracking 'X' in the gate lavel simulation

    but shortly after starting some debug at the output of the FPGA signals got 'X'.
    The manual way to find out why you see an X propagation is to go back in sim time and track down the FIRST source of X. Then find out the reason as to why that X is happening.
    FPGA enthusiast!



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    Re: Tracking 'X' in the gate lavel simulation

    Ok, I found a source - a missing statement in a reset block.

    I see in my simulation (waveform preview in Modelsim) that the half of the rising edge is blue and half of it is green. The falling edge is half red and half green (the vertical bar which depicts edge of the digital waveform is red at the top and green at the bottom). How to interpret this result of the simulation? The value of the signal between edges is green (=has got a value).
    This piece of logic is interfaced to the model of the SRAM memory.



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    Re: Tracking 'X' in the gate lavel simulation

    You've been here more than long enough to know that...

    A picture is worth way more than all that verbiage you posted and posting the code along with the picture would likely be much more likely to get an answer.



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  6. #6
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    Re: Tracking 'X' in the gate lavel simulation

    I find the "missing statement in a reset block" kind of creepy.
    Reset should be pin-applied signal and nothing but, else you
    may have a simulation that works and a physical result that
    doesn't, or not consistently.

    The small delay is probably some marched-out initial condition
    (saying that reset wasn't happening as completely as it has
    to).



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