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  1. #1
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    what pins The programming USB-jtag port and 8 pin JTAG header is connected to FPGA?

    Hello Everyone,

    I have many FPGA development/platform boards that can be programmed/configured by the USB-JTAG port available and also has a JTAG 8 pin connector too.
    1) why do we have two when we can program and get debug signals using same USB-JTAG port(It can be done in ZYBO(zynq board) ?

    I read many docs for this and understood that each FPGA has a TAP controller to communicate via JTAG. here i have plenty of questions that are not clear to me .

    1) Does this TAP controller work for both programming and debugging ? if yes then then how it decides to program or debug ?

    2) which one will be connected to TAP controller FPGA pins, USB-JTAG or 8 pin JTAG header ?

    3) There are other programming options like master SPI & BPI and slave too and also like QSPI/SD. they should be connected to FPGA pins on the PCB. I saw in a doc(UG470) for the signals for them and saw like they share most of FPGA pins(like JTAG signals) and additionally have there own dedicated signals too on FPGA. my question is how switching between the connections of QSPI/SD/JTAG happens near the FPGA to receive programming info depending upon mode pins.

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  2. #2
    Super Moderator
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    Bochum, Germany
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    Re: what pins The programming USB-jtag port and 8 pin JTAG header is connected to FPG

    The questions need to be answered specifically for FPGA family and dev board. A few general points though:

    The JTAG port of a FPGA can have different functions. Generic functions available with every FPGA are boundary scan and volatile configuration, also non-volatile configuration of flash based FPGA. Other functions (programming of connected memory, debug functions like Chipscope/Signaltap) are provided by software.

    Dev boards with on board USB-to-JTAG bridge respectively vendor specific JTAG adapter may provide an additional native JTAG port, e.g. to allow connection of other JTAG tools incompatible with the on-board adapter. In this case, a mux switches the FPGA JTAG port between both interfaces.

    Although programming of configuration memory, e.g. SPI flash, can be conveniently performed through FPGA JTAG functions, it may be desirable to have direct access to the SPI interface by an external connector.

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