Facing difficulty in executing the code for calling function using tri-state buffer

`resetall
`timescale 1ns/100ps

module ram_sp( 
			clk         , // Clock Input
			address     , // Address Input
			data        , // Data bi-directional
			cs          , // Chip Select
			we          , // Write Enable/Read Enable
			oe            // Output Enable
  	     ); 
  
  parameter DATA_WIDTH = 128 ;
  parameter ADDR_WIDTH = 128 ;
  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
  
  //--------------Input Ports----------------------- 
  input                  clk         ;
  input [ADDR_WIDTH-1:0] address     ;
  input                  cs          ;
  input                  we          ;
  input                  oe          ; 
  
  //--------------Inout Ports----------------------- 
  inout [DATA_WIDTH-1:0]  data       ;
  
  //--------------Internal variables---------------- 
  reg [DATA_WIDTH-1:0] data_out ;
  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
  reg                  oe_r;
  
  //--------------Code Starts Here------------------ 
  
  // Tri-State Buffer control 
  // output : When we = 0, oe = 1, cs = 1
     assign data = (cs && oe &&  ! we) ? data_out : 128'bz; 
  
  // Memory Write Block 
  // Write Operation : When we = 1, cs = 1
  always @ (posedge clk)
  begin : MEM_WRITE
     if ( cs && we ) 
	   begin
                mem[address] = data;
    	   end
  end
  
  // Memory Read Block 
  // Read Operation : When we = 0, oe = 1, cs = 1
  always @ (posedge clk)
  begin : MEM_READ
    if (cs &&  ! we && oe) 
		begin
      		     data_out = mem[address];
      		     oe_r = 1;
	        end 
     else begin
         oe_r = 0;
     end

  end

 endmodule

`resetall
`timescale 1ns/100ps
module ram_sp_tb;
  reg                  clk;
  reg  [127:0]           address;
  reg                  cs;
  reg                  we;
  reg                  oe; 
  wire [127:0]       data;
  reg [127:0]     data_in;
  integer              l;
	
	reg ge,en;
	reg [127:0] aesin;
	reg [127:0] daesin;
	reg [127:0] keyin;
	wire [127:0]aesout;
	wire [127:0]daesout;
	wire [127:0]keyout;

ram_sp uut( .clk(clk),         
		.address(address), 
		.data(data), 
		.cs(cs),
 		.we(we), 
		.oe(oe));

assign data = (we)?  data_in : 128'bz; 

initial begin  
	address = 128'h0;
	clk = 0;
	we = 0;
	cs = 0;
	oe = 0;
	ge=0;
forever 
#5 clk = ~clk; 
end 
begin 
#30   we = 1;
      cs = 1;
      data_in = 128'h00;
#20 
for (l=0; l<128; l=l+1)
begin
#10
address = address + 1;
data_in = data_in + 1;
end

	 we = 0;
         cs = 1;
         oe = 1;
	ge = 1;
	address = 128'h0;
	for (l=0; l<128; l=l+1)
	 begin 
	#10  address = address + 1;	
	end
aes uut (	.aesin(aesin),
 		.keyin(keyin),
		.clk(clk),
  		.keyout(keyout),
		.aesout(aesout)
	);


daes uut (	.daesin(daesin),
 		.keyin(keyin),
		 .clk(clk),
		.keyout(keyout), 
		.daesout(daesout)
	);

end
begin	
	tri0 aesin;
	tri1 daesout;
	wire ge;

	toplevel g1(aesin,i, en), g3(daesout, i, en);
	toplevel g2 (ge, i ,en);
	end
endmodule