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  1. #1
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    Facing difficult in executing the code for calling function using tri-state buffer

    Hello,

    Please help me include a tri state buffer to call two programs in a ram single port program such that my output is, ram reads the output of daes.v only when it is enabled 1 and writes from aes.v when it is 0. software used : CADENCE

    the codes are as follows.

    Ram source code:
    Code:
    `resetall
    `timescale 1ns/100ps
    
    module ram_sp( 
    			clk         , // Clock Input
    			address     , // Address Input
    			data        , // Data bi-directional
    			cs          , // Chip Select
    			we          , // Write Enable/Read Enable
    			oe            // Output Enable
      	     ); 
      
      parameter DATA_WIDTH = 128 ;
      parameter ADDR_WIDTH = 128 ;
      parameter RAM_DEPTH = 1 << ADDR_WIDTH;
      
      //--------------Input Ports----------------------- 
      input                  clk         ;
      input [ADDR_WIDTH-1:0] address     ;
      input                  cs          ;
      input                  we          ;
      input                  oe          ; 
      
      //--------------Inout Ports----------------------- 
      inout [DATA_WIDTH-1:0]  data       ;
      
      //--------------Internal variables---------------- 
      reg [DATA_WIDTH-1:0] data_out ;
      reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
      reg                  oe_r;
      
      //--------------Code Starts Here------------------ 
      
      // Tri-State Buffer control 
      // output : When we = 0, oe = 1, cs = 1
         assign data = (cs && oe &&  ! we) ? data_out : 128'bz; 
      
      // Memory Write Block 
      // Write Operation : When we = 1, cs = 1
      always @ (posedge clk)
      begin : MEM_WRITE
         if ( cs && we ) 
    	   begin
                    mem[address] = data;
        	   end
      end
      
      // Memory Read Block 
      // Read Operation : When we = 0, oe = 1, cs = 1
      always @ (posedge clk)
      begin : MEM_READ
        if (cs &&  ! we && oe) 
    		begin
          		     data_out = mem[address];
          		     oe_r = 1;
    	        end 
         else begin
             oe_r = 0;
         end
    
      end
    
     endmodule

    Ram testbench:
    Code:
    `resetall
    `timescale 1ns/100ps
    module ram_sp_tb;
      reg                  clk;
      reg  [127:0]           address;
      reg                  cs;
      reg                  we;
      reg                  oe; 
      wire [127:0]       data;
      reg [127:0]     data_in;
      integer              l;
    	
    	reg ge,en;
    	reg [127:0] aesin;
    	reg [127:0] daesin;
    	reg [127:0] keyin;
    	wire [127:0]aesout;
    	wire [127:0]daesout;
    	wire [127:0]keyout;
    
    ram_sp uut( .clk(clk),         
    		.address(address), 
    		.data(data), 
    		.cs(cs),
     		.we(we), 
    		.oe(oe));
    
    assign data = (we)?  data_in : 128'bz; 
    
    initial begin  
    	address = 128'h0;
    	clk = 0;
    	we = 0;
    	cs = 0;
    	oe = 0;
    	ge=0;
    forever 
    #5 clk = ~clk; 
    end 
    begin 
    #30   we = 1;
          cs = 1;
          data_in = 128'h00;
    #20 
    for (l=0; l<128; l=l+1)
    begin
    #10
    address = address + 1;
    data_in = data_in + 1;
    end
    
    	 we = 0;
             cs = 1;
             oe = 1;
    	ge = 1;
    	address = 128'h0;
    	for (l=0; l<128; l=l+1)
    	 begin 
    	#10  address = address + 1;	
    	end
    aes uut (	.aesin(aesin),
     		.keyin(keyin),
    		.clk(clk),
      		.keyout(keyout),
    		.aesout(aesout)
    	);
    
    
    daes uut (	.daesin(daesin),
     		.keyin(keyin),
    		 .clk(clk),
    		.keyout(keyout), 
    		.daesout(daesout)
    	);
    
    end
    begin	
    	tri0 aesin;
    	tri1 daesout;
    	wire ge;
    
    	toplevel g1(aesin,i, en), g3(daesout, i, en);
    	toplevel g2 (ge, i ,en);
    	end
    endmodule
    errors are: ncvlog -work worklib -cdslib /home/research1/17311d0615/AES/cds.lib -logfile ncvlog.log -errormax 15 -update -linedebug -status /home/research1/17311d0615/AES/128ram_tb.v
    ncvlog(64): 15.20-s031: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
    #30 we = 1;
    |
    ncvlog: *E,EXPEND (/home/research1/17311d0615/AES/128ram_tb.v,41|0): Expecting the keyword 'end' [12.1.3(IEEE 2001)].
    #10
    |
    ncvlog: *E,EXPEND (/home/research1/17311d0615/AES/128ram_tb.v,47|0): Expecting the keyword 'end' [12.1.3(IEEE 2001)].
    we = 0;
    |
    ncvlog: *E,EXPLPA (/home/research1/17311d0615/AES/128ram_tb.v,52|5): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
    cs = 1;
    |
    ncvlog: *E,EXPLPA (/home/research1/17311d0615/AES/128ram_tb.v,53|12): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
    oe = 1;
    |
    ncvlog: *E,EXPLPA (/home/research1/17311d0615/AES/128ram_tb.v,54|12): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
    ge = 1;
    |
    ncvlog: *E,EXPLPA (/home/research1/17311d0615/AES/128ram_tb.v,55|4): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
    address = 128'h0;
    |
    ncvlog: *E,EXPLPA (/home/research1/17311d0615/AES/128ram_tb.v,56|9): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
    #10 address = address + 1;
    |
    ncvlog: *E,EXPEND (/home/research1/17311d0615/AES/128ram_tb.v,59|1): Expecting the keyword 'end' [12.1.3(IEEE 2001)].
    end
    |
    ncvlog: *E,EXPENM (/home/research1/17311d0615/AES/128ram_tb.v,76|2): expecting the keyword 'endmodule' [12.1(IEEE)].
    ncvlog: Memory Usage - 21.3M program + 26.6M data = 47.9M total
    ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 41.7% cpu)

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  2. #2
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    Re: Facing difficult in executing the code for calling function using tri-state buffe

    These are Verilog semantic errors, caused by an entity structure violating Verilog rules. The compiler complains about the first unexpected keyword.

    In this case you have a begin statement outside a sequential block. Review a Verilog tutorial or design examples what's expected here.


    1 members found this post helpful.

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  3. #3
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    Re: Facing difficult in executing the code for calling function using tri-state buffe

    could you please help me to correct my code wherever necessary as am trying since morning and unable to correct them..



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