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CUVMUR error for VHDL code and Verilog testbench

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shreyakishore

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I am trying to test a VHDL code for 4x4 array multiplier and passing it through a Verilog testbench.
I am attaching all the code files I have used. I used a separate file to define all the component entities and then a main file for the multiplier.
Screenshot 2018-11-06 at 3.07.42 PM.png

Screenshot 2018-11-06 at 3.08.00 PM.png

Screenshot 2018-11-06 at 3.08.22 PM.png

The testbench is in Verilog code. I don't have much clue about Verilog and the testbench was provided to me.

Screenshot 2018-11-06 at 3.07.25 PM.jpg

On running the command ncverilog with the file names, I am getting this error.
error2 copy.png

I am at my wit's end trying to figure out the problem. I would be very grateful if someone can help me out with this.
 

There's no design unit named multiplier in your VHDL code.
 

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