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  1. #1
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    CUVMUR error for VHDL code and Verilog testbench

    I am trying to test a VHDL code for 4x4 array multiplier and passing it through a Verilog testbench.
    I am attaching all the code files I have used. I used a separate file to define all the component entities and then a main file for the multiplier.
    Click image for larger version. 

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ID:	149920

    Click image for larger version. 

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ID:	149921

    Click image for larger version. 

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ID:	149922

    The testbench is in Verilog code. I don't have much clue about Verilog and the testbench was provided to me.

    Click image for larger version. 

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ID:	149923

    On running the command ncverilog with the file names, I am getting this error.
    Click image for larger version. 

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ID:	149924

    I am at my wit's end trying to figure out the problem. I would be very grateful if someone can help me out with this.

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  2. #2
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    Re: CUVMUR error for VHDL code and Verilog testbench

    There's no design unit named multiplier in your VHDL code.



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  3. #3
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    Re: CUVMUR error for VHDL code and Verilog testbench

    The main vhdl code is multiplier.vhd



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  4. #4
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    Re: CUVMUR error for VHDL code and Verilog testbench

    The main vhdl code is multiplier.vhd
    The file name doesn't matter, the entity name is mul rather than multiplier.



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