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Entity and component with the same name in VHDL

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shaiko

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Hello,

Suppose I have an entity named: "some_entity".
Inside this entity I instantiate a component that's also named "some_entity"...

A real life example:
When an IP from Quartus is configured, the wizard asks us to give it a name. This will end up being the name of a wrapper that will instantiate the core logic with the native vendor component's name.
If the designer (accidentally or intentionally) choose the same name as the inner core the above scenario will happen...

Does the LRM have any protections against such a case ?
 

No protection as a component is a black box from the compiler point of view. You can direct the elaboration with a configuration to tell it which components map to each entity. Otherwise the tools will have their own rules how it searches for the entites. IIRC, Quartus first searches the work library (ie. the library you compiled "some_entity" in to) then other libraries.

In your instance, with no configuration, you probably have a recursive module - which is legal.
 
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    shaiko

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So such conduct won't cause an error ?
 

It depends if the recursion is limited or infinite. And tool rules.
Its not a compiler error, but may cause elaboration errors.
 
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    shaiko

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So such conduct won't cause an error ?
 

is the IP in it's own library? if so, there wouldn't be any name collisions unless you compile your HDL into the same library for some reason.
 
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