wtr
Full Member level 5
Hello all,
We've got a board where the test_leds have been routed terribly.
TEST_LEDS(9 downto 0) are wired in a scattered format
Looks something like this
(3)--------(8)
(8)--------(5)
(4)--------(2)
(9)--------(1)
(0)--------(7)
I want to be able to generate an alias name that can be assigned using slicing.
The following is the alias syntax rule
Where I want xxx to be test_led(0) & test_led(9) etc
I know the following works but it doesn't give me the std_logic_vector I want for slicing.
Regards
We've got a board where the test_leds have been routed terribly.
TEST_LEDS(9 downto 0) are wired in a scattered format
Looks something like this
(3)--------(8)
(8)--------(5)
(4)--------(2)
(9)--------(1)
(0)--------(7)
I want to be able to generate an alias name that can be assigned using slicing.
The following is the alias syntax rule
Code:
alias_declaration ::=
alias alias_designator [ : subtype_indication ] is name [ signature ] ;
alias_designator ::= identifier | character_literal | operator_symbol
Code VHDL - [expand] 1 alias led : std_logic_vector(TEST_LEDS'range) is xxx
Where I want xxx to be test_led(0) & test_led(9) etc
I know the following works but it doesn't give me the std_logic_vector I want for slicing.
Code VHDL - [expand] 1 2 alias led9 : std_logic is test_led(0); alias led8 : std_logic is test_led(9);
Regards