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  1. #1
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    VHDL Aliases advanced usecase of name signment

    Hello all,

    We've got a board where the test_leds have been routed terribly.

    TEST_LEDS(9 downto 0) are wired in a scattered format

    Looks something like this

    (3)--------(8)
    (8)--------(5)
    (4)--------(2)
    (9)--------(1)
    (0)--------(7)

    I want to be able to generate an alias name that can be assigned using slicing.

    The following is the alias syntax rule
    Code:
    alias_declaration ::=
    alias alias_designator [ : subtype_indication ] is name [ signature ] ;
    alias_designator ::= identifier | character_literal | operator_symbol
    Code VHDL - [expand]
    1
    
    alias led : std_logic_vector(TEST_LEDS'range) is xxx

    Where I want xxx to be test_led(0) & test_led(9) etc

    I know the following works but it doesn't give me the std_logic_vector I want for slicing.
    Code VHDL - [expand]
    1
    2
    
    alias led9 : std_logic is test_led(0);
    alias led8 : std_logic is test_led(9);

    Regards

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  2. #2
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    Re: VHDL Aliases advanced usecase of name signment

    For this, you'd probably be better off just creating a slv signal and assigning the leds in a more suitable order. You can only alias to existing objects.



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  3. #3
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    Re: VHDL Aliases advanced usecase of name signment

    I would either have a permutation function, do the permutation elsewhere at the top level, or do the permutation in the xdc file.



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  4. #4
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    Re: VHDL Aliases advanced usecase of name signment

    So,

    The following is allowed because TEST_LEDS object exists, even if we've switched range ascending/deceasing and sliced it.

    Code VHDL - [expand]
    1
    2
    
    alias leds : std_logic_vector(3 downto 0) is TEST_LEDS(3 downto 0);
    alias leds2 : std_logic_vector(3 downto 0) is TEST_LEDS(4 to 7);

    However one cannot create a """new""" object by concatenating a selection of objects?

    alias leds : std_logic_vector(7 downto 0) is TEST_LEDS(4 to 7) & TEST_LEDS(3 downto 0);

    An object is (a constant, variable signal or a file) <- basically stuff before the begin keyboard in architecture body.

    This is a shame.

    Was aware of the slv method, but was trying to do something clever/pushing the language.



  5. #5
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    Re: VHDL Aliases advanced usecase of name signment

    why not just create another signal? It really isnt any different to what you're doing.



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    Re: VHDL Aliases advanced usecase of name signment

    TrickyDicky,

    It's not about getting to the destination. IT's about the journey.



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  7. #7
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    Re: VHDL Aliases advanced usecase of name signment

    Sometimes, during the journey, an npc suggests adding a layer of indirection. Upon completing this quest you gain +1 wisdom.


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