What does this mean in RC?

liletian said:

Hi Guys

I got this info after the irun. Can anyone please explain?

Thanks

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Info    : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162]
        : Non_unate 'timing_sense' inferred between pin 'B' and 'S' in libcell 'ADDFHX1'.
Info    : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162]
        : Non_unate 'timing_sense' inferred between pin 'A' and 'S' in libcell 'ADDFHX1'.
 
[COLOR="silver"]- --------------------[/COLOR]
 
Info    : Promoting a setup arc to recovery. [LBR-30]
        : The asynchronous input pin is DFFNSRX2/RN
 
[COLOR="silver"]--------------------------[/COLOR]
 
Info    : Promoting a setup arc to recovery. [LBR-30]
        : The asynchronous input pin is DFFNSRX2/RN

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what does this mean?

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ThisIsNotSam said:

It's a benign message, saying that although the liberty file has a setup constraint on the reset pin, the tool will handle it as a recovery constraint (which is correct since it is a reset pin)

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liletian said:

Thanks for the message.
the following case is not recoverable, correct?



416373) Clock pin absent in sequential cell(s) (RSLATX4)
Warning : Missing clock pin in the sequential cell. [LBR-525]
: (sage-x_tsmc_cl018g_rvt_tt_1p8v_25c.lib, block starting at: 416773) Clock pin absent in sequential cell(s) (RSLATXL)


Info : Mismatch in unateness between 'timing_sense' attribute and the function. [LBR-155]
: 'timing_sense' attribute between pin 'WB' and 'RB' in libcell 'RF1R1WX2' is 'neg_unate', but unateness determined from function is 'non_unate'.

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ThisIsNotSam said:

this one is more severe but could still be ok. really hard to tell, the liberty format is too complex and the tool that generate the liberty might have used something that RTLCompiler can't understand or interpret. I would recommend reporting a few paths that use the aforementioned cell and checking if it looks reasonable

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liletian said:

how can I find the path with this cell? Is there an easy way to do it?

Thanks,

Click to expand...

ThisIsNotSam said:

I'd create a fake circuit that has this cell and a few inverters.

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