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Number of configuration bits used by design in Vivado

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msdarvishi

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Hi,



I am using Vivado 2017.3 targeting a Zedboard with a Zynq FPGA.



I have designed and implemented a design and generated the bitstream that works properly. I am wondering whether it is possible to decode the number of configuration bits in FPGA that are used by the implemented design in the Vivado tool or any corresponding output file. Is it possible to extract this information?



Thanks in advance for your help and support.



Bests,

Daryon
 

Yes enable the generation of the EBC and EBD files by adding -g essentialbits:yes to the Bistream generation.

The EBC file is the scanable configuration frames (frames that are not configured as memory, i.e. BRAM and LUT based RAM) configuration data and the EBD file contains masks for each bit that is essential for the design.

Write a script to count 1's in the EBD file and that should give you a good estimate of the number of required bits in your design.
 
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