ranaya
Advanced Member level 4
Hi All,
I want to compare power numbers of a synthesized design (based on umc65nm) with :
a. the existing cell library XOR gate and
b. A full custom made XOR targeted for low power (both meet x1 drive strength).
I also have the back end data for the cell library, so that I can perform transistor level simulation for existing one. When I ran a spice simulation (both custom and existing xors in schematic level, without layout parasitic), for many load/frequency conditions, the custom one is more energy efficient. After the layout, when I ran the custom one with parasitics against the existing one without parasitics, still the custom one is more energy efficient, however % is bit less than before (as obvious).
However the power numbers generated by the synthesis after the characterization of the custom cell, suggest that the existing one is more efficient than the custom one.
1. In the spice simulation, I calculate the average power for different loads/frequencies.
2. I did the R+C+CC parasitic extraction which results a huge netlist for the custom cell. Is it too much for digital library cell characterization ? Is "gate level" extraction sufficient for this ?
3. For the characterization, I used the same load/slew conditions used by umc65 for their xor. However I do not know how they extract the parasitics in their flow. I just want to make an apple-to-apple comparison.
Thanks in advance
ranaya
I want to compare power numbers of a synthesized design (based on umc65nm) with :
a. the existing cell library XOR gate and
b. A full custom made XOR targeted for low power (both meet x1 drive strength).
I also have the back end data for the cell library, so that I can perform transistor level simulation for existing one. When I ran a spice simulation (both custom and existing xors in schematic level, without layout parasitic), for many load/frequency conditions, the custom one is more energy efficient. After the layout, when I ran the custom one with parasitics against the existing one without parasitics, still the custom one is more energy efficient, however % is bit less than before (as obvious).
However the power numbers generated by the synthesis after the characterization of the custom cell, suggest that the existing one is more efficient than the custom one.
1. In the spice simulation, I calculate the average power for different loads/frequencies.
2. I did the R+C+CC parasitic extraction which results a huge netlist for the custom cell. Is it too much for digital library cell characterization ? Is "gate level" extraction sufficient for this ?
3. For the characterization, I used the same load/slew conditions used by umc65 for their xor. However I do not know how they extract the parasitics in their flow. I just want to make an apple-to-apple comparison.
Thanks in advance
ranaya