ravichandar
Newbie level 4
I have written a code for a multi bit shift register and there is a counter also in the same always_block for a different purpose.
Counter value is incremented on every clock cycle by 1 and saturates after reaching N no matter if i include the conditonal count block in the for loop or after the for loop. I am not able to figure out why?
Another question regarding the same logic block: If i were to use a generate statement, how do i separate the reset condition from the for loop?
something like this:
genvar i
generate
for (i =1; i<N;i++)
always_ff (@posedge clk, negedge reset)
<reset -condition> ---- giving error for multiple drivers.
else
< mem<= mem[i-1]; --- getting a complie time constant on LHS error.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 logic [W-1:0] mem [N:0]; logic [W+1:0] sum_act,sum_fin; logic [N+1:0] count; always_ff @(posedge clk, negedge reset) begin if(!reset) begin count <=0; mem <= '{default:{W{1'b0}}}; end else begin mem[0] <= in; for ( int i=1; i<= N; i=i+1) begin mem[i] <= mem[(i-1)]; if (count <= N) count <= count +1; end //for end //else end//always
Counter value is incremented on every clock cycle by 1 and saturates after reaching N no matter if i include the conditonal count block in the for loop or after the for loop. I am not able to figure out why?
Another question regarding the same logic block: If i were to use a generate statement, how do i separate the reset condition from the for loop?
something like this:
genvar i
generate
for (i =1; i<N;i++)
always_ff (@posedge clk, negedge reset)
<reset -condition> ---- giving error for multiple drivers.
else
< mem<= mem[i-1]; --- getting a complie time constant on LHS error.
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