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system verilog for loop in always_ff question

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ravichandar

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I have written a code for a multi bit shift register and there is a counter also in the same always_block for a different purpose.

Code Verilog - [expand]
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logic [W-1:0] mem [N:0];
  logic [W+1:0] sum_act,sum_fin;
  logic [N+1:0] count;
  
         
    always_ff @(posedge clk, negedge reset) begin
      if(!reset) begin
        count <=0;
        mem <= '{default:{W{1'b0}}};
           
      end  else begin
        mem[0] <= in;
          for ( int i=1; i<= N; i=i+1)  begin
          mem[i] <= mem[(i-1)];
      
        if (count <= N)
        count <= count +1;
          end //for
     end //else
    end//always

Counter value is incremented on every clock cycle by 1 and saturates after reaching N no matter if i include the conditonal count block in the for loop or after the for loop. I am not able to figure out why?

Another question regarding the same logic block: If i were to use a generate statement, how do i separate the reset condition from the for loop?

something like this:

genvar i
generate

for (i =1; i<N;i++)

always_ff (@posedge clk, negedge reset)

<reset -condition> ---- giving error for multiple drivers.

else
< mem<= mem[i-1]; --- getting a complie time constant on LHS error.
 
Last edited by a moderator:

ravichandar said:
Code: 
        if (count <= N)
        count <= count +1;
Counter value is incremented on every clock cycle by 1 and saturates after reaching N no matter if i include the conditonal count block in the for loop or after the for loop. I am not able to figure out why?
Click to expand...
Because that is exactly what you coded.

I think the problem here is not knowing what each statement does in the code due to not having learned the language.

if the value of count is less than or equal to N increment the value of count, otherwise do absolutely nothing.

You need to also think about changing the way you combine logic in a single always block. Unless the signals are closely related (i.e. they are dependent on each other) then I never combine different signals in the same always block in the same if statement. IMO having for loops around both stuff that is dependent on the index and stuff that isn't is a recipe for making mistakes and creating errors.

Another question regarding the same logic block: If i were to use a generate statement, how do i separate the reset condition from the for loop?
Click to expand...
see above, don't have code that shouldn't be auto replicated in a for loop.
 

Appreciate your reply. But it does not help at all except adding criticism. I did not intend to code this way. If was an accidental finding.Anyways, this is what i am thinking. If you can confirm that would be great.

count <=count+1; is a non-blocking assignment. If you have it in a for loop in always _ff on every clock edge, the loop is unrolled for the no. of iterations of the loop. If you have the loop riunning for 5 times, you have the code unrolled like this.

Code: 
count <= count+1;
count <= count+1;
count <= count+1;
count <= count+1;
count <= count+1;

Since all these evaluate to the same value and its non-blocking assignment, the count value increments by only 1. Had it been blocking, count value will reach N in the first cycle itself.

Regarding the usage of generate statement, i am still not clear on how to seperate the reset condition from the for-loop. I know it should not be in the for-loop and hence the multi driver issue. If you can show the example, that would be great.
 

I see you answered the first part of the question yourself. Yes that's how blocking statements work. It repeats the same assignment N times which does just nothing.

Regarding generate, it's not clear at all what you want to achieve. Of course the same assignment can't be repeated without causing a multiple driver error, except inside the same sequential block.

The shift register can be effectively implemented as done in post #1 loop construct.
 

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